Inverter: Static Characteristics

Introduction
The Inverter is ( NOT Gate) most
fundamental logic gate that performs a
Boolean operation on a single input
variable.
In this topic, we will examine the DC (static)
characteristics of various MOS inverter
circuits.
The logic symbol and the truth table of the
ideal inverter are shown In fig 5.1.

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 Introduction
Using the positive logic convention, the
Boolean(or Logic) value of “1” can be represented
by high voltage of VDD , and the Boolean value of
“0” can be represented by a low voltage 0.
The DC Voltage Transfer Characteristic (VTC) of
ideal inverter circuit is shown in fig. 5.2.
The voltage Vth is called the inverter threshold
voltage.
Note that for any input voltage between 0 to
Vth = VDD/2, the output voltage is equal to VDD.

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 Introduction

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 Introduction
Now we will see the general circuit
structure of an nMOS inverter.
And then after we will see the VTC for the
same inverter circuit.

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 Introduction
The general shape of the VTC in Fig. 5.4 is
qualitatively similar to that of the ideal
inverter transfer characteristic shown in
Fig. 5.2.
We identify two critical voltage points on
this curve, where the slope of the Vth(Vin)
characteristic becomes equal to -1, i.e.,

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 Introduction

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 Introduction
 VOH: Maximum output voltage when the output
level is logic " 1"
 VOL Minimum output voltage when the output
level is logic "0"
 VIL: Maximum input voltage which can be
interpreted as logic "0"
 VIH: Minimum input voltage which can be
interpreted as logic " 1"

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 Introduction
Noise Immunity and Noise Margins

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 Introduction
To illustrate the effect of noise on the circuit reliability,
we will consider the circuit consisting of three cascaded
inverters, as shown in Fig. 5.5.
Assume that all inverters are identical, and that the input
voltage of the first inverter is equal to VOH, i.e., a logic "
1.“
By definition, the output voltage of the first inverter will
be equal to VOL' corresponding to a logic "0" level.
Now, this output signal is being transmitted to the next
inverter input via an interconnect, which could be a
metal or polysilicon line connecting the two gates. Since
on-chip interconnects are generally prone to signal noise,
the output signal of the first inverter will be perturbed
during transmission.

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 Introduction

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 Introduction
These observations lead us to the definition
of noise tolerances for digital circuits,
called noise margins and denoted by NM.
The noise immunity of the circuit increases
with NM. Two noise margins will be defined:
the noise margin for low signal levels (NML)
and the noise margin for high signal levels
(NMH).

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 Introduction
The shape of voltage function is described
by the VTC.

The voltage perturbation can be assumed

as delta V noise and that is added in the
output voltage,

By using a simple first order Taylor series

expansion and by neglecting higher order
terms, we can express the output voltage
as,

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 Introduction
The DC power dissipation of an inverter circuit can
be calculated as the product of its power supply
voltage and the amount of current drawn from the
power supply during steady state.

Notice that the DC current drawn by the inverter

circuit may vary depending on the input and output
voltage levels. Assuming that the input voltage level
corresponds to logic "0“ during 50% of the operation
time and to logic " 1 " during the other 50%, the
overall DC power consumption of the circuit can be
estimated as follows:

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 Resistive –Load Inverter
The basic structure of the resistive-load inverter
circuit is shown in Fig. 5.7. As in the general
inverter circuit already examined in Fig. 5.3, an
enhancement-type nMOS transistor acts as the
driver device. The load consists of a simple linear
resistor, RL. The power supply voltage of this
circuit is VDD.
The drain current ID of the driver MOSFET is equal
to the load current IR in DC steady-state operation.
To simplify the calculations, the channel-length
modulation effect will be neglected in the
following, i.e., Lemda = 0. and VSB = 0

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 Resistive –Load Inverter

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 Resistive –Load Inverter
For input voltages smaller than the
threshold voltage VT0, the transistor is in
cut-off, and does not conduct any drain
current.

With increasing input voltage, the drain

current of the driver also increases, and the
output voltage Vout, starts to drop.
Eventually, for input voltages larger than
Vout+ VT0,the driver transistor enters the
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linear
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 Resistive –Load Inverter
The various operating regions of the driver
transistor and the corresponding input-
output conditions are listed in the following
table.

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 Resistive –Load Inverter
Figure 5.8 shows the voltage transfer
characteristic of a typical resistive-load
inverter circuit, indicating the operating
modes of the driver transistor and the
critical voltage points on the VTC.
Now, we start with the calculation of the
five critical voltage points, which determine
the steady-state input-output behavior of
the inverter.

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 Resistive –Load Inverter

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 Resistive –Load Inverter
Calculation of VOH
First, we note that the output voltage Vout is
given by

When the input voltage Vin is low, i.e., smaller

than the threshold voltage of the driver MOSFET,
the driver transistor is cut-off. Since the drain
current of the driver transistor is equal to the
load current, IR = ID = 0. It follows that the output
voltage of the inverter under these conditions is:

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 Resistive –Load Inverter
Calculation of VOL
To calculate the output low voltage VOL'
we assume that the input voltage is
equal to VOH i.e., Vin = VOH = VDD. Since
Vin – VT0 > Vout in this case, the driver
transistor operates in the linear region.
Also note that the load current IR is,

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 Resistive –Load Inverter
Using KCL for the output node, i.e., IR = ID
we can write the following equation:

This equation yields a simple quadratic in

VOL which is solved to find the value of the
output low voltage.

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 Resistive –Load Inverter
Note that of the two possible solutions of
(5.17), we must choose the one that is
physically correct, i.e., the value of the
output low voltage must be between 0 and
VDD. The solution
of (5.17) is given below. It can be seen that
the product (kn ,RL) is one of the important
design parameters that determine the value
of VOL

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 Resistive –Load Inverter
Calculation of VIL
By definition, VIL is the smaller of the two
input voltage values at which the slope of
the VTC becomes equal to (-1),i.e.,
dVout/dVin = - 1. Simple inspection of Fig.
5.8 shows that when the input is equal to
VIL, the output voltage (Vout) is only slightly
smaller than VOH. Consequently, Vout > Vin
– VT0, and the driver transistor operates in
saturation. We start our analysis by writing
the KCL for the output node.
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 Resistive –Load Inverter
To satisfy the derivative condition, we
differentiate both sides of (5.19) with
respect to Vin, which results in the
following equation:

Since the derivative of the output voltage

with respect to the input voltage is equal to
-1 at VIL, we can substitute dVout / dVin= -
1 in (5.20).
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 Resistive –Load Inverter
Solving (5.21) for VIL, we obtain

The value of the output voltage when the

input is equal to VIL can also be found by
substituting (5.22) into (5.19), as follows:

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 Resistive –Load Inverter
Calculation of VIH
VIH is the larger of the two voltage points
on VTC at which the slope is equal to (-1). It
can be seen from Fig. 5.8 that when the
input voltage is equal to VIH, the output
voltage Vout,, is only slightly larger than
the output low voltage VOL. Hence, Vout <
Vin – VT0, and the driver transistor operates
in the linear region. The KCL equation for
the output node is given below.

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 Resistive –Load Inverter
Differentiating both sides of (5.24) with
respect to Vin,, we obtain

Next, we can substitute dVout /dVi = - 1

into (5.25), since the slope of the VTC is
equal to (-1) also at V in= VIH

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 Resistive –Load Inverter
Solving (5.26) for VIH yields the following
expression.

Thus, we obtain two algebraic equations,

(5.24) and (5.27), for two unknowns, VIH
and Vout, To determine the unknown
variables, we substitute (5.27) into the
current equation given by (5.24) above.

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 Resistive –Load Inverter
The positive solution of this second-order
equation gives the output voltage Vout
when the input is equal to VIH.

Finally, VIH can be found by substituting

(5.29) into (5.27), as follows.

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 Resistive –Load Inverter
Power Consumption and Chip Area
The average DC power consumption of the
resistive-load inverter circuit is found by
considering two cases, Vin= VOL (low) and Vin =
VOH (high).
When the input voltage is equal to VOL, the driver
transistor is in cut-off. Consequently, there is no
steady-state current flow in the circuit (ID = IR =
0), and the DC power dissipation is equal to zero.
When the input voltage is equal to VOH on the
other hand, both the driver MOSFET and the load
resistor conduct a nonzero current.

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 Resistive –Load Inverter
Since the output voltage in this case is
equal to VOL the current drawn from the
power supply can be found as

Assuming that the input voltage is "low"

during 50% of the operation time, and
"high“ during the remaining 50%, the
average DC power consumption of the
inverter can be estimated as follows:

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 Inverter with n-type MOSFET Load
 In this section, we will introduce inverter circuits, which use an nMOS
transistor as the active load device, instead of the linear load resistor.
 The circuit configurations of two inverters with enhancement-type load
devices are shown in Fig. 5.11.
 Depending on the bias voltage applied to its gate terminal, the load
transistor can be operated either in the saturation region or in the linear
region.
 In addition, both types of inverter circuits shown in Fig. 5.11 suffer
from relatively high stand-by (DC) power dissipation; hence,
enhancement-load nMOS inverters are not used in any large-scale
digital applications.

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 Inverter with n-type MOSFET Load

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 Inverter with n-type MOSFET Load
Depletion-Load nMOS Inverter
Several of the disadvantages of the
enhancement-type load inverter can be
avoided by using a depletion-type nMOS
transistor as the load device.
The immediate advantages of
implementing this circuit configuration are:
(i) sharp VTC transition and better noise
margins, (ii) single power supply, and (iii)
smaller overall layout area.

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 Inverter with n-type MOSFET Load

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 Inverter with n-type MOSFET Load
 The circuit diagram of the depletion-load
inverter circuit is shown in Fig. 5.12(a), and a
simplified view of the circuit consisting of a
nonlinear load resistor and a non ideal switch
(driver) in shown in Fig. 5.12(b).
 The operating regions and the voltage levels of
the driver and the load transistors at critical
points are listed below.

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 Inverter with n-type MOSFET Load
 Equation of VOH
 When input Vin is smaller than driver threshold voltage
VT0, driver transistor is turned off, and drain current is
zero so
=0
The only solution is
VOH = VDD
 Equation of VOL
 When Vin =VOH, driver transistor operates in linear
region so that
=

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 Equation

  of VIL
 At Vin=VIL, driver is in saturation and load is at linear

At VIL, slope of VTC is -1 so taking derivative of above

equation w.r.t VIN we have
()=

Putting the condition =-1 at Vin=V IL we have

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 Inverter with n-type MOSFET Load
Equation

  of VIH
When input VIH slope of VTC is -1 and driver operates in linear
and load operates in saturation mode. Thus

Differentiating both sides w.r.t. Vin both side of above

equation, we have

=[
Substituting dVout/dVin=-1 and Vin=VOH we have

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 One important observation is that, unlike in the
enhancement-load inverter case, a sharp VTC
transition and larger noise margins can be
obtained with relatively small driver-to-load
ratios. Thus, the total area occupied by a
depletion-load inverter circuit with an acceptable
circuit performance is expected to be much
smaller than the area occupied by a comparable
resistive-load or enhancement-load inverter.

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 CMOS Inverter
which consists of an enhancement-type nMOS
transistor and an enhancement-type pMOS
transistor, operating in complementary mode (Fig.
5.16).
This configuration is called Complementary MOS
(CMOS).
The circuit topology is complementary push-pull in
the sense that for high input, the nMOS transistor
drives (pulls down) the output node while the
pMOS transistor acts as the load, and for low input
the pMOS transistor drives (pulls up) the output
node while the nMOS transistor acts as the load.

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 CMOS Inverter

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 CMOS Inverter

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  In Region A where Vin<VT0, the nMOS transistor is in Cut-off
and output voltage is equal to VOH=VDD.
 When input voltage is increased beyond V T0n nMOS starts
conducting in saturation mode (region B) and output voltage
starts decreasing. At VIL dVout/dVin=-1 located in region .
 As output voltage is further decreases pMOS enters into
saturation and at the boundary Region C as shown in figure
it is the inverter threshold voltage V out=Vin.
 As Vout falls below falls below Vin-VT0n, the nMOS starts
conducting in linear region and a critical voltage V IH reached
where dVout/dVin=-1 located in region D.
 In region E, when Vin> VDD+VT0p, pMOS cutoff and output is
VOL.

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 CMOS Inverter
The table below lists these regions and the
corresponding critical input and output
voltage levels.

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 CMOS Inverter
Equation
  of VIL
With Vin=VIL, pMOS operates in linear and nMOS in saturation and
thus

Now taking derivative both sides above equation w.r.t. Vin we

have

 Putting the conditions Vin=VIL and =-1 we have

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  Equation of VIH
At Vin=VIH, nMOS is in linear and pMOS is in saturation so
that

 Taking derivative w.r.t Vin both sides of above equation

and putting the conditions we have
2 and
putting Vin=VIH we have

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 CMOS Inverter
 Equation of Vth
At Vin=Vout=Vth, both nMOS and pMOS are in saturation
so that

Solving this we have

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 CMOS Inverter

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 Design of CMSO Inverter
For

  a given power supply VDD the nMOS and pMOS
transistor threshold voltages and desired threshold
voltage of inverter Vth, ratio kR can be found as

Or
Putting the condition for ideal inverter Vth=VDD/2 we have

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  For a symmetric inverter
so that

Or

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 CMOS Inverter
The noise margins NML and NMH for this
symmetric CMOS inverter are now
calculated using

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 Outcomes
From this unit, we come to know about
MOS inverters. The working of MOS
inverters and its different types.
The electrical properties as well as various
design of the MOS inverters can also be
understood.
The comparison of various designs of the
MOS inverters, advantages and
disadvantages of each inverters are also
understood.

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 Super Buffer
 Super buffer – A chain of inverters designed to drive a large
capacitive load with minimal signal propagation delay time
 A major objective of super buffer design

– Given the load capacitance faced by a logic gate, design a scaled

chain of N inverters such that the delay time between the logic gate
and the load capacitance node is minimized
– The design task is to determine the number of stages,(N), and
the optimal scale factor, α

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 Super buffer design
For the super buffer
– Cg: the input capacitance of the first stage inverter
– Cd: the chain capacitance of the first stage inverter
– The inverters in the chain are scaled up by a factor of α per stage
– Cload= αN+1Cg
– All inverters have identical delay of τ 0(Cd+ αCg)/(Cd+Cg)
• τ0: the per gate delay in the ring oscillator circuit with load capacitance (C d+Cg)

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