PROGRAMMABLE INTERVAL TIMER

8254
 Introduction:

 The 8254 programmable interval timer/counter is

similar to software designed timers and counters.

 It can be used for applications like real time clock,

am event counter, a square wave generator.

 It generates accurate time delays.

 The 8253/54 includes three identical 16 bit

counters that can operate independently in any
one of the 6 modes.
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PROGRAMMABLE INTERVAL TIMER
8254

• To operate a counter, a 16-bit count is loaded in

its register and, on command, it begins to
decrement the count until it reaches 0.

• At the end of the count, it generates the pulse

that can be used to interrupt MPU.

• The
BCD.
counter can count either in binary or

• InCPUaddition, a count can be read by the

while the counter is decrementing. 2
PROGRAMMABLE INTERVAL TIMER
8254
FEATURES:

 Three independent 16-bit down counters.

 8254 can operate with higher clock frequency range (DC to 8

MHz and 10 MHz for 8254-2).

 It is packaged in 24 pin DIP and requires a +5V power supply.

 Three counters are identical presettable, down counters and

can be programmed for either binary or BCD count.

 Counter can be programmed in six different modes.

 Compatible with all Intel and most other microprocessors.

 8253 has powerful command called READ BACK command 3

which allows the user to check the count value, programmed
mode and current mode and current status of the counter
 PROGRAMMABLE INTERVAL TIMER
8254

Architecture and signal descriptions:

 Three independent 16-bit counters, all these counters may be
independently controlled by programming the 3 internal
command word registers, thus possible to generate 3 totally
independent delays or maintain 3 independent counters
simultaneously.
 It has 8-bit, bidirectional data buffer interfaces internal circuit of
8253 to microprocessor system bus.
 Data is transmitted or received by the buffer upon the execution
of IN (reads data) or OUT(writes data to a peripheral) instruction.
 Read/write logic controls the direction of the data buffer
depending upon whether it is read or write operation.

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 I/O Interface

8254 Functional Description

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 PROGRAMMABLE INTERVAL TIMER
8254

 The block diagram of 8253/54 includes three counters, a data

bus buffer, Read/Write control logic, and a control register.
 Each counter has two input signals CLOCK and GATE and one
output signal OUT.
 CLK: The clock input is the timing source for each of the internal counters. It is
often connected to the PCLK signal from the bus controller.
 GATE: The gate input controls the operation of the counter in some modes.
 OUT: A counter output where the wave-form generated by the timer is
available.
Data Bus Buffer :
Thistri-state, bi-directional, 8-bit buffer is used to interface the
8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers. 6
3. Reading the count values.
 PROGRAMMABLE INTERVAL TIMER
8254
Read/Write Logic :
 The Read/Write logic has five signals : RD,WR,CS and the
address lines A0 and A1.
 In the peripheral I/O mode, the RD, and WR signals are
connected to IOR and IOW, respectively.
 In memory-mapped I/O, these are connected to MEMR and
MEMW.
 Address lines A0 and A1 of the CPU are usually connected to
lines A0 and A1 of the 8253/54, and CS is tied to a decoded address.
 The control word register and counters are selected according to
the signals on lines A0 and A1.

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 PROGRAMMABLE INTERVAL TIMER
8254

Read/Write Logic :
 A low on CS line enables the 8253. No operation will be
performed by 8253 till it
is enabled. Table below shows the selected operations for
various inputs of 8253:
CS RD WR A1 A0 selected operation
0 1 0 0 0 write counter 0
0 1 0 0 1 write counter 1
0 1 0 1 0 write counter 2
0 1 0 1 1 write control word
0 0 1 0 0 read counter 0
0 0 1 0 1 read counter 1
0 0 1 1 0 read counter 2
0 0 1 1 1 no operation
0 1 1 x x no operation 8

1 X x x x disabled
 PROGRAMMABLE INTERVAL TIMER
8254
Control Word Register :
 This register is accessed when lines A0 and A1 are at logic 1
 It is used to write a command word which specifies the counter to
be used (binary or BCD), its mode, and either a read or write
operation.
Counters :
 These three functional blocks are identical in operation. Each
counter consists of a single, 16 bit, pre-settable, down counter.
The counter can operate in either binary or BCD and its input,
gate and output are configured by the selection of modes stored
in the control word register.
 The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the
actual count in process. 9
 PROGRAMMABLE INTERVAL TIMER
8254
Operational Description:
 The complete functional definition of the 8253/54 is programmed by the
system
 software. Once programmed, the 8253/54 is ready to perform whatever
timing tasks it is assigned to accomplish.
Programming the 8253/54 :
 Each counter of the 8253/54 is individually programmed by writing a
control word into the control word register (A0 -A1 = 11).
 The Fig. shows the control word format.

 Bits SC1 and SC0 select the counter, bits RW1 and RW0 select the read,
write or latch command, bits M2,M1 and M0 select the mode of
operation and bit BCD decides whether it is a BCD counter or binary
counter.
 The complete functional definition of the 8253/54 is programmed by the
system
 software.
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 Once programmed, the 8253/54 is ready to perform whatever timing
tasks it is assigned to accomplish.
 Programmable interval Timer 8254

Each counter is individually programmed by writing a control word,

followed by the initial count.

The control word allows the programmer to select the counter, mode of
operation, binary or BCD count and type of operation (read/write).

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 Programmable interval Timer 8254
Programming the 8254

Each counter may be programmed with a count of 1 to FFFFH.

Each counter has a program control word used to select the way the
counter operates.
If two bytes are programmed, then the first byte (LSB) stops the
count, and the second byte (MSB) starts the counter with the new
count.

There are 6 modes of operation for each counter:

12 Mode0, Mode1, Mode2, MOde3, Mode4, Mode5
 Programmable interval Timer 8254
Programming the 8254
Modes of operation
 Mode 0: interrupt on terminal count.
The output becomes a logic 0 when the control word is written and
remains there until N plus the number of programmed counts.

 Mode 1: One-shot mode.

The G input triggers the counter to output a 0 pulse for count
clocks.Counter reloaded if G is pulsed again.
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 Programmable interval Timer 8254
Programming the 8254
Modes of operation
Mode 2: rate generator or divide by N counter
N is loaded as the count value, then after N pulses, the output becomes low
only for one clock cycle.
The cycle is repeated until reprogrammed or G pin set to 0.

 Mode 3: Generates a continuous square-wave with G set to 1.

If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

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 Programmable interval Timer 8253
Programming the 8254
Modes of operation
Mode 4: Software triggered one-shot (G must be 1).

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

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Trigger with count of 5

 Programmable interval Timer 8253I/O Interface

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 Programmable interval Timer 8254 I/O Interface
Read Operations

There are three possible methods for reading the counters:

• a simple read operation
• the Counter Latch Command
• the Read-Back Command

Simple read operation :

• The Counter which is selected with the A1, A0 inputs, the CLK input of
the selected Counter must be inhibited by using either the GATE input
or external logic.
• Otherwise, the count may be in the process of changing when it is read,
giving an17undefined result.
 Programmable interval Timer 8253I/O Interface

Counter Latch Command:

• SC0, SC1 bits select one of the

three Counters
• two other bits, D5 and D4,
distinguish this command from a
Control Word
• If a Counter is latched and then,
some time later, latched again before
the count is read, the second Counter
Latch Command is ignored. The
count read will be the count at the
time the first Counter Latch
Command was issued.
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PROGRAMMING
CONTROL WORD FORMAT

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

0 0 1 1 0 1 0
0

= 34H(Mode 2)

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

0 0 1 1 0 1
1 0
= 36H(Mode 3) 19
CONTROL WORD
 SELECT SC0 SC1 OPE RATION

COUNTER BIT
DEFINITION 0 0 Select channel 0
0 1 Select channel 1
1 0 Select channel 2
1 1 Illegeal
RL0 RL1 OPE RATION
 READ\LOAD BIT
DEFINITION 0 0 Latch Counter
0 1 Read\Load(LSB)
1 0 Read\Load(MSB)
1 1 Read\Load LSB
first then 20
MSB
MODE
M2 M1 M0 SELECTED
MODE

0 0 0 MODE 0
0 1 MODE 1 MODE SELECT BIT DEFINITION
X 0 0 MODE 2
X 1 1 MODE 3
1 0 MODE 4
0 1 MODE 5
0

1 BCD OPERATION
1
0 Hex Count
1 BCD Count HEX\BCD BIT DEFINITION

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RATE GENERATOR
MOV AL,34H Move the command word to A register
OUT 16,AL Output it to control register

MOV AL,04H Move 04 to A register

OUT 10,AL Output the value to counter 0

MOV AL,00H Move 00 to A register

OUT 10,AL Output the value to content 0

HLT Halt the program execution

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SQUARE WAVE
MOV AL,36H Move the command word to A
register
OUT 16,AL Output it to control register
MOV AL,04H Move 04 to A register

OUT 10,AL Output the value to counter 0

MOV AL,00H Move 00 to A register

OUT 10,AL Output the value to content 0

HLT Halt the program execution

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 I/O Interface
16550 Programmable Communications Interface:
• 16550 , A universal asynchronous receiver/transmitter (UART).
• it capable of operating speed: 0 to 1.5M Baud (Baud is # of bits
transmitted/sec, including start, stop, data and parity).
•It includes:
- A programmable Baud rate generator.
- Separate FIFO buffers for input and and output data (16
bytes each).
Asynchronous serial data:
Asynchronous serial data are transmitted and received without a
clock or timing signal.

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Two 10-bit frames of asynchronous serial data, start bit, 7 data bit,
parity & stop bit.
 I/O Interface
16550 functional description:

• this device is available as 40-pin DIP( dual in-line package) or as a 44-pin

PLCC ( plastic lead less chip)

• two separate sections are responsible for data communications

- Receiver & Transmitter

• can function :
- simplex: transmit only,
eg:FM radio station
-half-duplex: transmit and receive but not
simultaneously
eg: CB( citizen band) station
- full-duplex: transmit and receive
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simultaneously
eg : telephone
 I/O Interface

•main feature, has internal receiver & transmitter FIFO memories,

each 16 Bytes deep.

• the UART, requires attention only from the microprocessor after

receiving 16 bytes of data

• it holds 16 bytes before the microprocessor must wait for the ‘

transmitter.

• the FIFO makes UART ideal when interfacing to high speed systems

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 I/O Interface

The 16550 can control a modem through

and .
the modem is called the data set
the 16550 is called the data terminal.

16550 Pin function:

A0, A1 and A2: Select an internal register for

programming and data transfer.

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 I/O Interface
 : Address strobe used to latch address and chip select. Not
needed on Intel systems - connected to ground.
 : Clock signal from Baud rate generator in transmitter.
 CS0, CS1, : Chip selects must all be active enable the 16550
UART
 : Clear to send -- indicates that the modem or data set is ready
to exchange information. (Used in half-duplex to turn the line around).
 D7-D0: The data bus pins are connected to the microprocessor data
bus.
 : The data carrier detect -- used by the modem to signal the
16550 that a carrier is present.
 DDIS: Disable driver output -- set to 0 to indicate that the
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microprocessor is reading data from the UART. Used to change
direction of data flow through a buffer.
 I/O Interface

 : Data set ready is an input to 16550, indicates that the modem

(data set) is ready to operate.

 : Data terminal ready is an output, indicates that the data

terminal (16550) is ready to function.

 INTR: Interrupt request is an output to the microprocessor, used to

request an interrupt.
Receiver error, Data received, Transmit buffer empty

 MR: Master reset , connect to system RESET

 : User defined output pins for modem or other device.

 RCLK: Receiver clock, clock input to the receiver section of the UART.
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Always 16X the desired receiver Baud rate.
 I/O Interface
 : Ring indicator input , set to 0 by modem to indicate telephone is
ringing.

 RD, : Read inputs (either can be used), cause data to be read from the
register given by the address inputs

 :Request-to-send, signal to modem, indicating UART

wishes to send data.

SIN, SOUT: Serial data pins, in and out.

 : Receiver ready, used to transfer received data
via DMA techniques.

 :Transmitter ready, used to transfer transmitter data

via DMA
 WR, 30 :Write (either can be used) , connects to microprocessor
write signal to transfer commands and data to 16550.

XIN, XOUT: Main clock connections -- a crystal oscillator can be used.

 I/O Interface

Programming 16550:
• the programming is a two part process
- initialization dialog
- operational dialog

Initializing 16550:
•Initialization dialog, occurs after a hardware or software reset,
Consists of two parts
- line control register
- baud rate generator
must be programmed

•Line control
31 register selects: number of stop & parity bit( even or odd)

•Baud rate generator: programmed with a divisor that determine the

baud rate of the transmission section
 I/O Interface

Line control register:

• programmed by outputting information to I/O ports 011
• Right most 2 bits, selects the number of transmitted data bits
(5,6,7or 8)

• Stop bits: S = 1, 1.5 stop bits used for 5 data bits, 2 used for 6, 7 or
8.
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• next 3 bits: ST(stick), P and PE used to send even or odd parity, to
send no parity or to send a 1 or a 0 in the parity bit position for all
data.
 I/O Interface

•SB = 1 , used to send a break to be transmitted on SOUT.

A break is at least two frame of logic 0 data.
software is responsible for timing the transmission,
33 to end the break SB return to logic 0

•DL = 1, enables programming of the baud rate divisor.

 I/O Interface

Programming the baud rate:

Baud rate generator is programmed with a divisor that sets
baud rate of transmitter.

• Baud rate generator is programmed at 000 and 001 ( A2,A!,A0).

Port 000 used to hold least significant part, 001 most
significant part

Value used depends on external clock/crystal frequency.

For 18.432MHz crystal :
- 10,473 divisor value 110 band rate,
- 30 divisor value gives 38,400 baud

Note : the actual number programmed into baud rate generator causes,
34 a clock that is 16 times the desired baud rate
to produce
eg : if 240 is programmed into baud rate divisor,
Baud rate = 18.432 MHz/(16X240) = 4800 baud.
 I/O Interface

FIFO control register for 16550:

• register enable the transmitter & receiver and clears the transmitter
& receiver FIFO.
• provides control for 16550 interrupts

Sending serial data :

line status register, contains the information about
- error conditions
35 - state of the transmitter & receiver

• the register is tested before a byte is transmitted or can be received

 I/O Interface

Suppose a program wants to send data out SOUT.

•It needs to pool the TH bit to determine if transmitter is ready to
receive data.

Receiving serial data:

•To receive information, the DR bit is tested.

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 I/O Interface

UART error:
Operation:
It is also a good idea to check for errors.

•Parity error: Received data has wrong error, transmission bit flip due to
noise.

•Framing error: Start and stop bits not in their proper places.
This usually results if the receiver is receiving data at the incorrect baud
rate.

•Overrun error: Data has overrun the internal receiver FIFO buffer.
Software is failing to read the data from UART before the FIFO is full.

•( BI )Break
37 indicator bit: Software should check for this as well, i.e. two
consecutive frames of 0s.
 I/O Interface

Examples, 16550 interfaced to the 8088 at ports 00F0H – 00F7H

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 I/O Interface

•Here port F3H accesses the line control register

•F0H & F1H access the baud rate divisor register

• after the line control register & baud rate divisor are programmed ,
still it is not ready to function

• program the FIFO control register, at port F2H

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