CPEN6115

DIGITAL SYSTEM

Design at Register Transfer Level

 Register Transfer Level (RTL)
• A digital system is a sequential logic system constructed with flip‐
flops and gates.
• To specify a large digital system with a state table is
very difficult, because the number of states would be
enormous.
• Large Digital system design – modular approach
– modular : constructed from digital device, e.g. register, decoder,
multiplexer etc.
• Register Transfer operation
– The information flow and processing perform on the data stored in register
• RTL is specified by the following three components:
– The set of register in the system
– The operation that are performed on the data stored in the register
– The control that supervises the sequence of operation in the system
 REGISTER
• Register is constructed from F.F. and gates
• 1 F.F. => 1 bit register
• N F.F. => n bit resister
• Register can perform set, cleared, or
complement
 Data Processing in Register
• Performed in parallel during one clock
• The result may replace previous data or
transferred to another register
• For example
– counter
– Shift register
 Statements of RTL
• Transfer : R2←R1
• Conditional statement :
– if (T1=1) then (R2 ← R1)
– if(T1=1) then (R2 ← R1, R1 ← R2)
• Other
– R1 ←R1+R2
– R3 ←R3+1
– R4 ←shr R4
– R5 ← 0
 Algorithmic State Machine
• Logic design can be divided into two part
– The digital circuits that perform the data
processing operation
– Control circuits that determines the sequence in
which the various actions are performed
 Algorithmic State Machine (ASM)

• A special flowchart that has been developed

specifically to define digital hardware algorithms
• Resembles a conventional flowchart, but is
interpreted somewhat differently.
– conventional : sequential
– ASM:
• sequence of even
• timing relationship between the states of sequential controller
• even occurs while going from one state to the next
• Three basic elements: state box, decision box,
conditional box
 State box

ASM chart state box

 Decision box

ASM chart decision box

 Conditional box

ASM chart conditional box

ASM block
ASM chart and state diagram
 Timing consideration
• Major difference between conventional flow chart and a
ASM chart is in interpreting the time relation among the
various operation
• ASM considers the entire block as one unit.
ASMD CHART
ASMD CHART
 DESIGN EXAMPLE
• Two JK Flip-Flops E and F.
• A 4-bits binary counter A (A3,A2,A1 and A0).
• A start signal S (starting by clearing A and F).
• S = 1, increment counter.
• A2 and A3 determine the sequences of operations
 If A2 = 0, E is clear to 0, count continues
 If A2 = 1, E is set to 1, then if A3 = 0, the count continues, but if A3 = 1, F is set
to 1 on next clock pulse and system stops counting.
 Then if S = 0, the system remains in the initial state, but if S = 1, the operation
cycle repeats.

 Either E is cleared and control stays in state S-1 (A2 = 0) or

 E is set and control stays in state S-1 (A2 A3 = 10) or
 E is set and control goes to state S-2 (A2 A3 = 11).
DESIGN EXAMPLE
DESIGN EXAMPLE
Datapath and controller for
design example
Register transfer‐level description of
design example
LOGIC DIAGRAM