Thietbikhatrinh

1.
Registers and Memory

Registers
• Common sequential device: registers.
– They’re a good example of sequential analysis and design.
– They are also frequently used in building larger sequential circuits.
• Registers hold larger quantities of data than individual flip-flops.
– Registers are central to the design of modern processors.
– There are many different kinds of registers.
– We’ll show some applications of
these special registers.
Điện Tử Số 2 2
What good are registers?
• Flip-flops are limited because they can store only one bit.
– We had to use two flip-flops for our two-bit counter examples.
– Most computers work with integers and single-precision floating-
point numbers that are 32-bits long.
• A register is an extension of a flip-flop that can store multiple bits.
• Registers are commonly used as temporary storage in a processor.
– They are faster and more convenient than main memory.
– More registers can help speed up complex calculations.
A basic register
• Basic registers are easy to build. We can store multiple
bits just by putting a bunch of flip-flops together!
• A 4-bit register from LogicWorks, Reg-4, is on the right,
and its internal implementation is below.
– This register uses D flip-flops, so it’s easy to store
data without worrying about flip-flop input equations.
– All the flip-flops share a common CLK and CLR signal.
Adding a parallel load operation
• The input D3-D0 is copied to the output Q3-Q0 on every clock cycle.
• How can we store the current value for more than one cycle?
• Let’s add a load input signal LD to the register.
– If LD = 0, the register keeps its current contents.
– If LD = 1, the register stores a new value, taken from inputs D3-D0.
LD Q(t+1)
0 Q(t)
1 D3-D0
Clock gating
• We could implement the load ability by playing games with the CLK
input, as shown below.
– When LD = 0, the flip-flop C inputs are held at 1. There is no
positive clock edge, so the flip-flops keep their current values.
– When LD = 1, the CLK input passes through the OR gate, so the flip-
flops can receive a positive clock edge and can load a new value from
the D3-D0 inputs.
Clock gating is bad
• This is called clock gating, since gates are added to the clock signal.
• There are timing problems similar to those of latches. Here, LD must
be kept at 1 for the correct length of time (one clock cycle) and no
longer.
• The clock is delayed a little bit by the OR gate.
– In more complex scenarios, different flip-flops in the system could
receive the clock signal at slightly different times.
– This “clock skew” can lead to synchronization problems.
A better parallel load
• Another idea is to modify the flip-flop D inputs and not the clock signal.
– When LD = 0, the flip-flop inputs are Q3-Q0, so each flip-flop just
keeps its current value.
– When LD = 1, the flip-flop inputs are D3-D0, and this new value is
“loaded” into the register.
Shift registers
• A shift register “shifts” its output once every clock cycle.
Q0(t+1) = SI
Q1(t+1) = Q0(t)
Q2(t+1) = Q1(t)
Q3(t+1) = Q2(t)
• SI (Serial Input) is an input that supplies a new bit to shift “into” the register.
• For example, if on some positive clock edge we have:
SI = 1
Q0-Q3 = 0110
then the next state will be:

Q0-Q3 = 1011
• The current Q3 (0 in this example) will be lost on the next cycle.
Shift direction
Q0(t+1) = SI
Q1(t+1) = Q0(t)
Q2(t+1) = Q1(t)
Q3(t+1) = Q2(t)
Present Q0-Q3 SI Next Q0-Q3

• The circuit and example make it look like the register shifts “right.”
ABCD X XABC
• But it really dependsPresent

on yourQinterpretation
3-Q0 SI of theQbits.
Next 3-Q0 If you consider Q3 to
be the most significant bit instead, then
DCBA CBAX is shifting in the opposite
X the register
direction!
Shift registers with parallel load
• We can add a parallel load, just like we did for regular registers.
– When LD = 0, the flip-flop inputs will be SIQ0Q1Q2, so the register
shifts on the next positive clock edge.
– When LD = 1, the flip-flop inputs are D0-D3, and a new value is loaded
into the shift register, on the next positive clock edge.
Shift registers in LogicWorks
• Here is a block symbol for the Shift Reg-4 from LogicWorks. The
implementation is shown on the previous page, except the LD input here
is active-low instead.
Serial data transfer
• One application of shift registers is converting between “serial data”
and “parallel data.”
• Computers typically work with multiple-bit quantities.
– ASCII text characters are 8 bits long.
– Integers, single-precision floating-point numbers, and screen pixels
are up to 32 bits long.
• But sometimes it’s necessary to send or receive data serially, or one bit
at a time. Some examples include:
– Input devices such as keyboards and mice.
– Output devices like printers.
– Any serial port, USB or Firewire device transfers data serially.
– Recent switch from Parallel ATA to Serial ATA in hard drives.
Receiving serial data
• To receive serial data using a shift register:
– The serial device is connected to the register’s SI input.
– The shift register outputs Q3-Q0 are connected to the computer.
• The serial device transmits one bit of data per clock cycle.
– These bits go into the SI input of the shift register.
– After four clock cycles, the shift register will hold a four-bit word.
• The computer then reads all four bits at once from the Q3-Q0 outputs.
serial device
shift register computer
Sending data serially
• To send data serially with a shift register, you do the opposite:
– The CPU is connected to the register’s D inputs.
– The shift output (Q3 in this case) is connected to the serial device.
• The computer first stores a four-bit word in the register, in one cycle.
• The serial device can then read the shift output.
– One bit appears on Q3 on each clock cycle.
– After four cycles, the entire four-bit word will have been sent.
computer
serial device
shift register
Registers in Modern Hardware
• Registers store data in the CPU

• Used to supply values to the ALU.
• Used to store the results.
• If we can use registers, why bother with RAM?
CPU GPR's Size L1 Cache L2 Cache
Pentium 4 8 32 bits 8 KB 512 KB
Athlon XP 8 32 bits 64 KB 512 KB
Athlon 64 16 64 bits 64 KB 1024 KB
Pow erPC 970 (G5) 32 64 bits 64 KB 512 KB
Itanium 2 128 64 bits 16 KB 256 KB
MIPS R14000 32 64 bits 32 KB 16 MB
Answer: Registers are expensive!

• Registers occupy the most expensive space
on a chip – the core.
• L1 and L2 are very fast RAM – but not as
fast as registers.
Registers summary
• A register is a special state machine that stores multiple bits of
data.
• Several variations are possible:
– Parallel loading to store data into the register.
– Shifting the register contents either left or right.
– Counters are considered a type of register too!
• One application of shift registers is converting between serial
and parallel data.
• Most programs need more storage space than registers provide.
– We’ll introduce RAM to address this problem.
• Registers are a central part of modern processors
RAM (Random Access Memory)
• Sequential circuits all depend upon the presence of memory.
– A flip-flop can store one bit of information.
– A register can store a single “word,” typically 32-64 bits.
• Random access memory, or RAM, allows us to store even larger amounts
of data. Today we’ll see:
– The basic interface to memory.
– How you can implement static RAM chips hierarchically.
• This is the last piece we need to put together a computer!
Introduction to RAM
• Random-access memory, or RAM, provides large quantities of temporary
storage in a computer system.
• Remember the basic capabilities of a memory:
– It should be able to store a value.
– You should be able to read the value that was saved.
– You should be able to change the stored value.
• A RAM is similar, except that it can store many values.
– An address will specify which memory value we’re interested in.
– Each value can be a multiple-bit word (e.g., 32 bits).
• We’ll refine the memory properties as follows:
A RAM should be able to:

- Store many words, one per address
- Read the word that was saved at a particular address
- Change the word that’s saved at a particular address
Picture of memory
• You can think of computer memory as being one Address Data
big array of data. 00000000
– The address serves as an array index. 00000001
00000002
– Each address refers to one word of data.
.
• You can read or modify the data at any given
memory address, just like you can read or .
modify the contents of an array at any given .
index. .
• If you’ve worked with pointers in C or C++, then .
you’ve already worked with memory addresses. .
.
.
.
.
FFFFFFFD
FFFFFFFE
FFFFFFFF
Block diagram of RAM
2k x n memory
CS WR Memory operation
k n 0 x None
ADRS OUT
n
DATA 1 0 Read selected word
CS 1 1 Write selected word
WR
• This block diagram introduces the main interface to RAM.

– A Chip Select, CS, enables or disables the RAM.
– ADRS specifies the address or location to read from or write to.
– WR selects between reading from or writing to the memory.
 To read from memory, WR should be set to 0.
OUT will be the n-bit value stored at ADRS.
 To write to memory, we set WR = 1.
DATA is the n-bit value to save in memory.
• This interface makes it easy to combine RAMs together, as we’ll see.
Memory sizes
• We refer to this as a 2k x n memory.
– There are k address lines, which can specify one of 2k addresses.
– Each address contains an n-bit word.
2k x n memory
k n
ADRS OUT
n
DATA
CS
WR
• For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits long.
– The RAM would need 24 address lines.
– The total storage capacity is 224 x 16 = 228 bits.
Size matters!
• Memory sizes are usually specified in numbers of bytes (8 bits).
• The 228 -bit memory on the previous page translates into:
228 bits / 8 bits per byte = 225 bytes
• With the abbreviations below, this is equivalent to 32 megabytes.
Prefix Base 2 Base 10

K Kilo 210 = 1,024 103 = 1,000
M Mega 220 = 1,048,576 106 = 1,000,000
G Giga 230 = 1,073,741,824 109 = 1,000,000,000
• To confuse you, RAM size is measured in base 2 units, while hard drive size is
measured in base 10 units.
– In this class, we’ll only concern ourselves with the base 2 units.
Typical memory sizes
Address Data
• Some typical memory capacities:
00000000
– PCs usually come with 128-256MB RAM.
00000001
– PDAs have 8-64MB of memory. 00000002
– Digital cameras and MP3 players can have .
32MB or more of storage. .
• Many operating systems implement virtual .
memory, which makes the memory seem larger .
than it really is. .
– Most systems allow up to 32-bit addresses. .
This works out to 232, or about four billion, .
different possible addresses. .
.
– With a data size of one byte, the result is
.
apparently a 4GB memory!
FFFFFFFD
– The operating system uses hard disk space
FFFFFFFE
as a substitute for “real” memory.
FFFFFFFF
Reading RAM
• To read from this RAM, the controlling circuit must:
– Enable the chip by ensuring CS = 1.
– Select the read operation, by setting WR = 0.
– Send the desired address to the ADRS input.
– The contents of that address appear on OUT after a little while.
• Notice that the DATA input is unused for read operations.
2k x n memory
k n
ADRS OUT
n
DATA
CS
WR
Writing RAM
• To write to this RAM, you need to:
– Enable the chip by setting CS = 1.
– Select the write operation, by setting WR = 1.
– Send the desired address to the ADRS input.
– Send the word to store to the DATA input.
• The output OUT is not needed for memory write operations.
2k x n memory
k n
ADRS OUT
n
DATA
CS
WR
Static memory
• How can you implement the memory chip?
• There are many different kinds of RAM.
– We’ll start off discussing static memory, which is most commonly
used in caches and video cards.
– Later we mention a little about dynamic memory, which forms the
bulk of a computer’s main memory.
• Static memory is modeled using one latch for each bit of storage.
• Why use latches instead of flip flops?
– A latch can be made with only two NAND or two NOR gates, but a
flip-flop requires at least twice that much hardware.
– In general, smaller is faster, cheaper and requires less power.
– The tradeoff is that getting the timing exactly right is a pain.
Starting with latches
• To start, we can use one latch to store each bit. A one-bit RAM cell is shown here.
• Since this is just a one-bit memory, an ADRS input is not needed.

• Writing to the RAM cell:
– When CS = 1 and WR = 1, the latch control input will be 1.
– The DATA input is thus saved in the D latch.
• Reading from the RAM cell and maintaining the current contents:
– When CS = 0 or when WR = 0, the latch control input is also 0, so the latch just
maintains its present state.
– The current latch contents will appear on OUT.
My first RAM
• We can use these cells
to make a 4 x 1 RAM.
• Since there are four
words, ADRS is two bits.
• Each word is only one
bit, so DATA and OUT
are one bit each.
• Word selection is done
with a decoder attached
to the CS inputs of the
RAM cells. Only one cell
can be read or written
at a time.
• Notice that the outputs
are connected together
with a single line!
Connecting outputs together
The “C” in LogicWorks

means “conflict.”
Those funny triangles
• The triangle represents a three-state buffer.

• Unlike regular logic gates, the output can be one of three different
possibilities, as shown in the table.
EN IN OUT
0 x Disconnected
1 0 0
1 1 1
• “Disconnected” means no output appears at all, in which case it’s safe to

connect OUT to another output signal.
• The disconnected value is also sometimes called high impedance or Hi-Z.
Connecting three-state buffers together
• You can connect several three-state
buffer outputs together if you can
guarantee that only one of them is
enabled at any time.
• The easiest way to do this is to use a
decoder!
• If the decoder is disabled, then all the
three-state buffers will appear to be
disconnected, and OUT will also appear
disconnected.
• If the decoder is enabled, then exactly
one of its outputs will be true, so only
one of the tri-state buffers will be
connected and produce an output.
• The net result is we can save some wire
and gate costs. We also get a little more
flexibility in putting circuits together.
Bigger and better
• Here is the 4 x 1 RAM
once again.
• How can we make a
“wider” memory with
more bits per word, like
maybe a 4 x 4 RAM?
• Duplicate the stuff in
the blue box!
A 4 x 4 RAM
• DATA and OUT are now each four bits long, so you can read and write
four-bit words.
Bigger RAMs from smaller RAMs
• We can use small RAMs as building blocks for making larger memories,
by following the same principles as in the previous examples.
• As an example, suppose we have some 64K x 8 RAMs to start with:
– 64K = 26 x 210 = 216, so there are 16 address lines.
– There are 8 data lines.
16
8 8
Making a larger memory
• We can put four 64K x 8 chips
together to make a 256K x 8 8
memory.
• For 256K words, we need 18 16
address lines.
– The two most significant
address lines go to the
decoder, which selects one of
the four 64K x 8 RAM chips.
– The other 16 address lines are
shared by the 64K x 8 chips.
• The 64K x 8 chips also share WR
and DATA inputs.
• This assumes the 64K x 8 chips
have three-state outputs.
8
Analyzing the 256K x 8 RAM
• There are 256K words of memory,
spread out among the four smaller 8
64K x 8 RAM chips.
• When the two most significant 16
bits of the address are 00, the

bottom RAM chip is selected. It
holds data for the first 64K
addresses.
• The next chip up is enabled when
the address starts with 01. It
holds data for the second 64K
addresses.
• The third chip up holds data for
the next 64K addresses.
• The final chip contains the data of
the final 64K addresses.
8
Address ranges
16 11 1111 1111 1111 1111 (0x3ffff)

to
11 0000 0000 0000 0000 (0x30000)
10 1111 1111 1111 1111 (0x2ffff)

to
10 0000 0000 0000 0000 (0x20000)
01 1111 1111 1111 1111 (0x1ffff)

to
01 0000 0000 0000 0000 (0x10000)
00 1111 1111 1111 1111 (0x0ffff)

to
8 00 0000 0000 0000 0000 (0x00000)
Making a wider memory
• You can also combine smaller chips to make wider memories, with the
same number of addresses but more bits per word.
• Here is a 64K x 16 RAM, created from two 64K x 8 chips.
– The left chip contains the most significant 8 bits of the data.
– The right chip contains the lower 8 bits of the data.
8 8
16
8 8
Summary
• A RAM looks like a bunch of registers connected together, allowing

users to select a particular address to read or write.
• Much of the hardware in memory chips supports this selection process:
– Chip select inputs
– Decoders
– Tri-state buffers
• By providing a general interface, it’s easy to connect RAMs together to
make “longer” and “wider” memories.
2. Giới thiệu công nghệ
IC khả trình
Công nghệ IC khả trình
• Realisation as AND-OR: • Realisation as OR-AND:
F1=xy+xy’z+x’yz F1=((x’+y’) (x’+y+z’)
(x+y’+z’))’
x y z x y z
F1 F1
42
Programmable logic array
• PLA
Programmable
And
Input
plane
Or Output
plane
43
Programmable logic array
• PLA
44
Programmable Array Logic
• PAL
Programmable
And
Input
plane
Fixed
Or Output
plane
45
Programmable Array Logic
46
Complex Programmable Logic Devices
• CPLD
47
Complex Programmable Logic Devices
• Các công nghệ lập trình

PROM: Lập trình 1 lần
EPROM, flash, EEPROM: lập trình nhiều lần
Non-volatile
48
Ví dụ: PROM
Vcc Vcc Vcc Vcc Fuse
After manufacturing
Address
2-to-4 Decoder
2
MSB
2
LSB
2-to-4 Mux
49 Data
Ví dụ: PROM
Vcc Vcc Vcc Vcc
After programming
Address
2-to-4 Decoder
2
MSB
2
LSB
2-to-4 Mux
50 Data
Field-programmable Gate Array
• FPGA: XC40xx Routing viaLong
switching
lines matrices
I/O I/O I/O I/O

I/O
SM SM SM SM
CLB CLB CLB

I/O
SM SM SM SM
CLB CLB CLB

I/O
SM SM SM SM
51
• Cấu tạo của một CLB (Configurable Logic Block)
16x1 G
LUT: GQ
FF
Bool-function
of 4
G
variables
16x1
F
LUT: FQ
FF
Bool-function
of 4
variables F
52
• FPGA: Switching Matrix SM
Pass
TOR
53
• Các loại kết nối:
54
• Công nghệ lập trình:
SRAM-based:
Volatile
Reprogrammble
Antifuse
Non-volatile
Programmed only-one
IP security
55
Field-Programmable Gate Array (FPGA)
• Hãng cung cấp FPGA hàng đầu thế giới
Công ty Xilinx: http://www.xilinx.com/
Công ty Altera: http://www.altera.com/
Công ty Lattice Semiconductor:
http://www.latticesemi.com/
Công ty Actel: http://www.actel.com/
Công ty Crypress: http://www.cypress.com/
Công ty Atmel: http://www.atmel.com/
Công ty QuickLogic: http://www.quicklogic.com/
56
Ưu điểm
57
Ưu điểm
• FPGA vs Custom ASIC
FPGAs are more flexible
FPGAs are more cost effective for small quantities
ASICs have higher densities
• FPGA vs Parallel Computer
FPGAs are more cost effective
FPGAs are smaller
Parallel Computers are easier to program
58
FPGA vs. ASIC Cost
ASIC: High volumes needed to recover design cost
Total FPGA .09µ

cost FPGA .13µ
ASIC .09µ ASIC cost/part
is lower
ASIC Design
Cost is much ASIC .13µ
higher
(and increasing)!!
For each technology advance,

Volume
crossover volume moves higher Courtesy: Richard Sevcik, Xilinx
59
Ứng dụng của công nghệ IC khả trình
• Aerospace & Defense
• Automotive
• Consumer
• Digital Video Technologies
• Industrial/Scientific & Medical
• Test & Measurement
• Wired Communications
• Wireless Communications
60
61
62
63
64
65
66
67
68
69
3. Ngôn ngữ VHDL
Giới thiệu về VHDL
• VHDL = VHSIC Hardware Description Language
• VHSIC = Very High Speed Integrated Circuit
• Là ngôn ngữ lập trình dùng để mô tả hoạt động của hệ
thống số
• Được quy định trong chuẩn IEEE 1076 từ năm 1983
• Các ngôn ngữ mô tả phần cứng khác:
Verilog
Abel
71
library IEEE; -- Su dung thu vien chuan IEEE
use IEEE.STD_LOGIC_1164.ALL; --Su dung tat ca cac thanh phan trong goi STD_LOGIC_1164
entity hex2led is
Port ( HEX : in std_logic_vector(3 downto 0);
LED : out std_logic_vector(6 downto 0));
end hex2led;
-- Khai bao hoat dong cua hex2Led 6
architecture Behavioral of hex2led is 3 5
2 Entity 4
begin HEX 1 3
hex2led 2
LEX
with HEX SELect 0
LED<= "1111001" when "0001", --1 1
"0100100" when "0010", --2 0
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
end Behavioral;
72
Ví dụ 1
• Thiết kế mạch ‘Test’ với 3 đầu vào 8-bit (In1, In2,
In3) và hai đầu ra 1 bit (Out1, Out2). Out1=‘1’ khi
In1=In2 và Out2=‘1’ khi In1 = In3
Test
Compare
In1 Out1
A
EQ
B
In2
Compare
A
In3 EQ Out2
B
73 Test là một khối gồm 2 bản copy của khối compare

Ví dụ 1
Thiết kế khối compare dùng mạch tổ hợp
Compare
A[0] XNOR
A
B[0]
A[1] AND
EQ
B[1] EQ
B
A[7]
B[7]
74
Ví dụ 1
• Thiết kế khối compare dùng VHDL ‘Entity’ xác định giao diện
với bên ngoài của khối cần thiết kế
- -Eight bit comparator

entity Compare is
port( A,B: in bit_vector(0 to 7);
EQ: out bit);
end Compare; đầu vào và ra được gọi là port
architecture Behav1 of Compare is
begin ‘Architecture’ miêu tả hoạt động
EQ <= ‘1’ when (A=B) else ‘0’; và cấu trúc bên trong của
end Behav1;
khối cần thiết kế
Chú ý:
-Một entity có thể có nhiều architecture, mỗi architecture là một
cách thể hiện khác nhau của cùng một chức năng
- Các Ports là vector có chiều: vào (in), ra (out), hoặc cả vào cả ra (inout)
75
Component và Instantiation
• Biểu diễn Test bằng VHDL
entity Test is
port( In1,In2,In3: in bit_vector(0 to 7);
Out1,Out2: out bit);
end Test;
architecture Struct1 of Test is

component Comparator is
port( X,Y: in bit_vector(0 to 7); 2 bản copy của cùng một
Z: out bit); component
end component; ‘Comparator’
begin
Compare1: Comparator port map (X=>In1, Y=>In2, Z=>Out1);
Compare2: Comparator port map (X=>In1,Y=>In3,Z=>Out2);
end Struct1;
Chú ý:
- Hai bản comparator chạy song song với nhau !!!
76 - Đây là architecture miêu tả cấu trúc của entity Test
Cấu hình (Configuration)
• Khi một entity có nhiều architectures, ta sẽ xử dụng architecture nào?
• Làm thế nào để gắn ‘Components’ với ‘Entities’?
-- Configuration information: architecture selection

-- and component-entity binding
configuration Build1 of Test is

for Struct1
for Compare1: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
for others: Comparator use entity Compare(Behav1)
port map (A => X, B => Y, EQ => Z);
end for;
end for;
end Build1;
77
Khai báo Entity và Architecture
ENTITY:
entity Entity_name is
port(Signal_name: in Signal_type;
Signal_name: out Signal_type);
end Entity_name;
ARCHITECTURE:
architecture Architecture_name of Entity_name is

Khai báo các tín hiệu cục bộ;
Khai báo các components;
begin
Các câu lệnh;
78 end Architecture_name;
Khai báo component
COMPONENT:
component Component_name is
port( Signal_name: in Signal_type;
Signal_name: out Signal_type);
end component;
Khai báo copy của COMPONENT :
Instance_name: component Component_name

port map (Signal_list);
Hoặc cách thứ 2, copy trực tiếp:
Instance_name: entity Entity_name(Architecture_name)

79
Khai báo cấu hình
CONFIGURATION:
configuration Config_name of Entity_name is

for Architecture_name
for Instance_name: Component_name use entity
Entity_name(Architecture_name)
end for;
end for;
end Config_name;
80
Ví dụ 2
• Biểu diễn cổng AND bằng VHDL
A
Y
B
C
-- 3-input AND gate
entity AND3 is
port ( A,B,C: in bit;
Y: out bit);
end AND3;
architecture RTL of AND3 is

begin
Y <= ‘1’ when ((A=‘1’) and (B=‘1’) and (C=‘1’)) else ‘0’;
end RTL;
81
Ví dụ 2
• Biểu diễn cổng OR bằng VHDL
A
Y
B
C
-- 3-input OR gate
entity OR3 is
port ( A,B,C: in bit;
Y: out bit);
end OR3;
architecture RTL of OR3 is

begin
Y <= ‘0’ when ((A=‘0’) and (B=‘0’) and (C=‘0’)) else ‘1’;
end RTL;
82
Ví dụ 2
• Biểu diễn cổng INV bằng VHDL
A Y
-- INV gate
entity INV is
port ( A: in bit;
Y: out bit);
end INV;
architecture RTL of INV is

begin
Y <= ‘1’ when (A=‘0’) else ‘0’;
end RTL;
83
Ví dụ 3
• Thiết kế bộ MUX 2-1 dùng VHDL
A
Y
B
S
entity MUX21 is
port ( A,B,S: in bit;
Y: out bit);
end MUX21;
architecture Behav of MUX21 is

begin
Y <= A when (S=‘1’) else B;
end Behav;
84
Ví dụ 3
A
Y
architecture Struct of MUX21 is B
signal U,V,W : bit;
component AND2 is S
port ( X,Y: in bit;
Z: out bit);
end component;
component OR2 is A
port ( X,Y: in bit; W
Z: out bit);
S Y
end component;
component INV is U V
port ( X: in bit;
Z: out bit); B
end component;
begin
Gate1: INV port map (X=>S,Z=>U);
Gate2: AND2 port map (X=>A,Y=>S,Z=>W);
Gate3: AND2 port map (X=>U,Y=>B,Z=>V);
Gate4: OR2 port map (X=>W,Y=>V,Z=>Y);
85 end Struct;
Ví dụ 3
• Giả sử ta muốn sử dụng các cổng AND, OR và INV ở
ví dụ 2 trong MUX21
configuration Use3InputGates of MUX21 is
for Behav Entities
end for; A
Y
for Struct B
for Gate1:INV use entity INV(RTL) C
port map (A=>X,Y=>Z);
end for; A Y
for All:AND2 use entity AND3(RTL)
port map (A=>X,B=>Y,C=>’1’,Y=>Z);
end for;
for Gate4:OR2 use entity OR3(RTL) Components
port map (A=>X,B=>Y,C=>’0’,Y=>Z);
X
end for; Z
end for;
Y
end Use3InputGates;
X Z
86
Tạo Testbench
• Testbench là entity dùng để mô phỏng và kiểm tra thiết kế
entity Testbench is A
end Testbench; Y
B MUX21
Testbench không có port S
architecture BehavTest of Testbench is

Signal In1,In2,Select,Out : bit;
begin
mux21_copy: entity MUX21(Behav) port map (In1, In2, Select, Out);
Thu: process is
begin
In1<=‘0’;In2<=‘1’;Select<=‘0’; wait for 20 ns;
Select<=‘1’; wait for 20 ns;
In1<=‘1’;In2<=‘0’; wait for 20 ns;
...
end process;
end BehavTest;
87
Tín hiệu và các kiểu dữ liệu:
Các kiểu dữ liệu đã được định nghĩa
Ví dụ về khai báo các kiểu số nguyên:
type Year is range 0 to 99;
type Memory_address is range 65535 downto 0;
Ví dụ về khai báo các kiểu số thực

type Probability is range 0.0 to 1.0;
type Input_level is range -5.0 to 5.0;
Khai báo bit_vector, giá trị được đặt trong dấu nháy kép
constant State1: bit_vector(4 downto 0) := “00100”;
MSB, bit 4 LSB
Kiểu chuỗi String là một chuỗi ký tự characters; giá trị của nó

được đặt trong dấu nháy kép
constant Error_message: string
:= “Unknown error: ask your poor sysop for help”;
88
ARCHITECTURE test OF test IS
ARCHITECTURE test OF test IS
BEGIN
SIGNAL a : REAL;
PROCESS(X)
BEGIN
VARIABLE a : INTEGER;
a <= 1.0; --Ok 1
BEGIN
a <= 1; --error 2
a := 1; --Ok 1
a <= -1.0E10; --Ok 3
a := -1; --Ok 2
a <= 1.5E-20; --Ok 4
a := 1.0; --error 3
a <= 5.3 ns; --error 5
END PROCESS;
END test;
END test;
89
Kiểu Time là kiểu vật lý:
type Time is range implementation_defined
units
fs; Primary unit:
ps = 1000 fs; resolution limit
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us; Secondary units
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
Được sử dụng rất nhiều trong chạy mô phỏng

wait for 20 ns;
constant Sample_period: time := 2 ms;
constant Clock_period: time := 50 ns;
90
Các kiểu dữ liệu của người sử dụng
Người sử dụng có thể định nghĩa kiểu vật lý như sau:
type Length is range 0 to 1E9
units Primary unit:
um; resolution limit
mm = 1000 um;
m = 1000 mm; Metric secondary units
km = 1000 m;
mil = 254 um;
inch = 1000 mil;
foot = 12 inch; Imperial secondary units
yard = 3 foot;
end units;
91
Standard logic
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE memory IS
CONSTANT width : INTEGER := 3;
CONSTANT memsize : INTEGER := 7;
TYPE data_out IS ARRAY(0 TO width) OF std_logic;
TYPE mem_data IS ARRAY(0 TO memsize) OF data_out;
END memory;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.memory.ALL;
ENTITY rom IS
PORT( addr : IN INTEGER;
data : OUT data_out;
cs : IN std_logic);
END rom;
92
Standard logic
ARCHITECTURE basic OF rom IS
CONSTANT z_state : data_out := (‘Z’, ‘Z’, ‘Z’, ‘Z’);
CONSTANT x_state : data_out := (‘X’, ‘X’, ‘X’, ‘X’);
CONSTANT rom_data : mem_data :=
( ( ‘0’, ‘0’, ‘0’, ‘0’),
( ( ‘0’, ‘0’, ‘0’, ‘1’),
( ( ‘0’, ‘0’, ‘1’, ‘0’),
( ( ‘0’, ‘0’, ‘1’, ‘1’),
( ( ‘0’, ‘1’, ‘0’, ‘0’),
( ( ‘0’, ‘1’, ‘0’, ‘1’),
( ( ‘0’, ‘1’, ‘1’, ‘0’),
( ( ‘0’, ‘1’, ‘1’, ‘1’) );
BEGIN
ASSERT addr <= memsize
REPORT “addr out of range”
SEVERITY ERROR;
data <= rom_data(addr) AFTER 10 ns WHEN cs = ‘1’ ELSE
data <= z_state AFTER 20 ns WHEN cs = ‘0’ ELSE
data <= x_state AFTER 10 ns;
END basic;
93
Các họ CPLD/FPGA của Xilinx
94
95
A Decade of Progress
1000x
• 200x More Logic

XC4000 & Virtex-4
 Plus memory, Spartan
µP etc. 100x
CLB Capacity
• 40x Faster Speed
Virtex-II &
Virtex-II Pro
• 50x Lower Power Power per MHz Virtex &
Price Virtex-E
• 500x Lower Cost
10x
Spartan-2
XC4000 Spartan-3
1x
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
Courtesy: Richard Sevcik, Xilinx
96
• Họ Virtex:
 Virtex-4:
 2004, 1.2 V, 90nm
 500 MHz, low power
 200.000 logic cells, DSP, PowerPC
 Thay thế ASIC, ASSP
 Virtex-II Pro /X
 2002, 1.5 V, 130nm
 400 MHz
 3K to 99K logic cells + DSP, PowerPC
97
• Họ Virtex:
 Virtex-II
 2001, 1.5 V, 150nm
 300 MHz
 3K to 99K logic cells
 Virtex /E
 1998/1999, 2.5 /1.8 V, 220 / 180 nm
 150/ 200 MHz
 3K to 70K logic cells
98
• Họ Spartan:
 Spartan-3/E /L
2003, 1.5 V, 90nm
300 MHz
5M gates
99
• Họ Spartan:
 Spartan-3/E /L
2003, 1.5 V, 90nm
300 MHz
5M gates
100
• CPLD- Họ Coolrunner
 CoolRunner-II
 1.8V, 180 nm
 303 MHz
 32-512 macrocells
 Ultra Low power
 CoolRunner-XPLA3
 3.3 V
 200 MHz
 Low power
101
• CPLD- Họ XC9500
 XC9500XV
 2.5 V
 250 MHz
 Low cost
 XC9500XL
 3.3 V
 200 MHz
 Low cost
 XC9500
 5 V, 200 MHz
 Low cost
102
Bài tập 1: Thiết kế bộ nhớ
• Thiết kế bộ nhớ cho một hệ thống vi xử lý 8 bít (microprocessor - µ P) có dung
lượng tổng cộng là 32K x 8
 Trong đó: vùng bộ nhớ ROM có dung lượng là 8K x 8, vùng bộ nhớ RAM tiếp
sau vùng nhớ ROM và chiếm phần dung lượng còn lại.
 Sử dụng bộ nhớ ROM có dung lượng: 8K x 8 (ROM 27C64)
 Sử dụng bộ nhớ RAM có dung lượng: 8K x 8 (RAM 62C64)
 Sử dụng vi mạch giải mã địa chỉ 74LS138 và các vi mạch cổng khác (nếu cần)
• Yêu cầu: SV trình bày sơ đồ mạch và bản đồ địa chỉ của bộ nhớ được thiết kế trên
tối đa 2 mặt giấy A4 (mỗi SV làm bài tối đa trên 1 tờ giấy A4)
103
Bài tập 2
• Thiết kế mạch điều khiển đèn giao thông theo yêu cầu
sau đây:
Thời gian đèn đỏ: 25 s = txanh + tvàng
Thời gian đèn vàng: tvàng = 5 s
Thời gian đèn xanh: txanh = 20 s
104

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1.

Registers and Memory

• Common sequential device: registers.

– They’re a good example of sequential analysis and design.

– They are also frequently used in building larger sequential circuits.

• Registers hold larger quantities of data than individual flip-flops.

– Registers are central to the design of modern processors.

– There are many different kinds of registers.

– We’ll show some applications of

these special registers.

– We had to use two flip-flops for our two-bit counter examples.

– Most computers work with integers and single-precision floating-

point numbers that are 32-bits long.

• A register is an extension of a flip-flop that can store multiple bits.

• Registers are commonly used as temporary storage in a processor.

– They are faster and more convenient than main memory.

– More registers can help speed up complex calculations.

then the next state will be:

• The current Q3 (0 in this example) will be lost on the next cycle.

Present Q0-Q3 SI Next Q0-Q3

• But it really dependsPresent

shift register computer

• Registers store data in the CPU

Answer: Registers are expensive!

A RAM should be able to:

• This block diagram introduces the main interface to RAM.

228 bits / 8 bits per byte = 225 bytes

• With the abbreviations below, this is equivalent to 32 megabytes.

Prefix Base 2 Base 10

• Since this is just a one-bit memory, an ADRS input is not needed.

The “C” in LogicWorks

• The triangle represents a three-state buffer.

• “Disconnected” means no output appears at all, in which case it’s safe to

bits of the address are 00, the

16 11 1111 1111 1111 1111 (0x3ffff)

10 1111 1111 1111 1111 (0x2ffff)

01 1111 1111 1111 1111 (0x1ffff)

00 1111 1111 1111 1111 (0x0ffff)

• A RAM looks like a bunch of registers connected together, allowing

• Các công nghệ lập trình

I/O I/O I/O I/O

CLB CLB CLB

CLB CLB CLB

Total FPGA .09µ

For each technology advance,

73 Test là một khối gồm 2 bản copy của khối compare

- -Eight bit comparator

architecture Struct1 of Test is

-- Configuration information: architecture selection

configuration Build1 of Test is

architecture Architecture_name of Entity_name is

Khai báo copy của COMPONENT :

Instance_name: component Component_name

Hoặc cách thứ 2, copy trực tiếp:

Instance_name: entity Entity_name(Architecture_name)

configuration Config_name of Entity_name is

-- 3-input AND gate

architecture RTL of AND3 is

architecture RTL of OR3 is

architecture RTL of INV is

architecture Behav of MUX21 is

Testbench không có port S