Review

• Basic I/O interface chip

INPUT OUTPUT
– 74LS244: Two 4-bit buffers
1G 1A 1Y
– 74LS245: Bidirectional transceiver
L L L
L H H
H X Z

ENABLE DIRECTION OPERATION

CONTROL

G DIR
L L B Data to A Bus
L H A Data to B bus
H X Isolation
• 74LS373: 8 bit latch

INPUTS OUTPUT
OC C D Q
L H H H
L H L L
L L x Q0
H x x Z
 I/O port addressing
FFFFF
• Memory mapped
Memory
Memory
Space
I/O
FFFFFH 00000

Memory
• I/O mapped
FFFFH
I/O
0
 Data transfer mode
• Three ways of exchanging data
between CPU and I/O
– Polling routine mode
– Interrupt mode
– Direct memory Access (DMA) mode
Chapter 7 Programmable
interface and application
 Objectives
• Feature of programmable chips,
internal structure and function of pins
• To design application circuit with these
chips
• To master the interrupts and deeply
understand the I/O interface
 Key terms
• Acknowledge(ACK) 接收
• Baud-rate 波特率
• CTS 清除发送
• DSR 数据装置就绪
• Edge-sensitive 边缘触发
• Handshaking 握手信号
• Parallel I/O 并行 I/O 口
• Serial I/O 串行 I/O 口
• Synchronous 同步的
• UART 通用异步收发机
 7.1 The 8255 Parallel data transfer
interface
• Parallel I/O
– All data bits are sent or received at the same
time
• 8255
– Programmable parallel interface
– Three data ports A,B,C, one control unit
– Widely used in many microcomputer and PC.
Interface of 8255
A1 A0 Port

0 0 A
0 1 B
1 0 C
1 1 Control

Effect address of Port A?

Port B? Port C?

Port A: A0H
Port B: A1H
Port C: A2H
 True table

CS RD WR A1 A0 Operation

0 1 0 0 0 Write Port A
0 1 0 0 1 Write Port B
0 1 0 1 0 Write Port C
0 1 0 1 1 Write Control Unit
0 0 1 0 0 Read Port A
0 0 1 0 1 Read Port B
0 0 1 1 0 Read Port C
0 0 1 1 1 No operation
 Working mode
• Three working modes
– Mode 0
– Mode 1
– Mode 2
• Decided by Mode word
– MOV AL, 98H
– OUT 0A3H, AL
 Mode 0:Basic input/output
• Caused automatically by RESET with all
ports for input.
• Each port can be individually programmed
as input or output.
• Port C is divided into two 4-bit halves,
directionally independent.
• Input data is not latched, but output data is
latched.
 Example
• What mode word is needed to program
port A for input, port B for output and
both halves of port C for input?

• 1 0 0 1 1 0 0 1 B=99H
Mode 1: Strobe for input/output
• Transferring I/O data to or from a specified
port in conjunction with strobe or
‘handshaking’ signals.

• Port A and B can be programmed for input or

output.

• Data are latched in both directions.

• Port C generates or accepts ‘handshaking’

signals for port A and Port B
 Example
• STB: Strobe Input
– Logic ‘low’ will load data
into the input latch.
• IBF: Input Buffer Full
– Logic ‘high’ indicates
that the data has been
load into the input latch.
• INTR: Interrupt request
– Logic ‘high’ could be
used to interrupt the
CPU.
• Mode word: B6H or
BDH
 Example
OBF: Output Buffer Full
Logic ‘low’ indicates that the
CPU has written data out to
the specified port.
ACK: Acknowledge input
Logic ‘low’ indicates that
data from specified port has
been accepted.
INTR: Interrupt request
Logic ‘high’ could interrupt
CPU.
Mode Word:84H or 8AH
 Mode 2: Strobe for bidirectional I/O

• Port A used as bidirectional bus I/O.

• Port C used for handshaking and general

purpose I/O.

• Port B used as an input port or output port

in mode 0 or mode 1.
 Example
Mode 2 and Mode 2 and
Mode 0 Input Mode 0 Output
Application-AD conversion

Configuration:
•8255 Mode 0
•Port A used for connection
•Port B used for visual
indication.
•Port C used for control
Base address: 40H
Port A: 40H
Port B: 41H
Port C:42H
Control word: 43H
 8255 initialization:

MOV AL, 91H; 1001 0001B, mode 0, A in, B out, CL in, CH out

OUT 43H, AL; sent to control word

MOV AL, 90H ; 1001 0000B, WR and RD of ADC are both 1

OUT 42H, AL; sent to Port C

 Program
VCON PROC FAR
MOV AL, 80H ; 1000 0000B, let WR to be 0
OUT 42H, AL ; sent WR to ADC and start to input analog signal
MOV AL, 90H ;let WR to be 1
OUT 42H, AL ; sent WR to ADC and stop the input
EOC: IN AL, 42H ; read the data from Port C
AND AL, 1 ; test bit-0 (INT signal from ADC)
JNZ EOC ; wait for the end of conversion
MOV AL, 10H ; let RD to be 0
OUT 42H,AL ; set RD to the ADC, so could read data from ADC
IN AL, 40H ; start to read from Port A
OUT 41H, AL ; output the data received from Port A to Port B
MOV AH, AL ; save the data in AH
MOV AL, 90H ; 1001 0000B, let WR and RD to be 1
OUT 42H, AL ; send WR and RD to ADC, end of conversion
RET
VCON END
 Review
• 8255
– Parallel data transfer interface
– Three data ports
– Three working mode
Basic input/output
Strobe for input/output
Strobe for bidirectional input/output
 7.2 The 8251 serial data transfer
interface
• Serial I/O
– 1 bit is transmitted at a time
– Less lines are needed
– Suitable for long distance communication
• 8251
– Universal Synchronous/Asynchronous Receiver
and Transmitter
– Programmable I/O interface
Block diagram
• Data bus transfer: 3-state, bidirectional
buffer.
• Control logic
– Receive the control signal
– C/D: inform the 8251 that the
information on the Data bus is either
data or control word or status
information
• Modem Control
– Control signals for interface to modem
• Transmit Buffer
– Accepts parallel data from Data Bus
buffer and converts it to a serial bit
stream and output it by TxD
• Transmit control
– Manage all activities associated with the
transmission of serial data
• Receive buffer
– Accepts serial data and convert it to
parallel format
• Receiver Control
– Manage all activities related to receiver
Pins
• DB7~DB0: Connect with DB of
CPU
• CLK: Used for internal device
timing
• CS: Chip-Select. Logic 0 on this line
enables data communication
between the CPU and the USART
• Reset: Logic 1 makes chip reset
 Read and Write logic
• CS: connect with IO/M and address decoder of CPU
• C/D: connect with an address line of CPU
• RD: connect with RD of CPU
• WR: connect with WR of CPU

CS C/D RD WR Operation
0 0 0 1 Read data from 8251
0 1 0 1 Read status from 8251
0 0 1 0 Write data to 8251
0 1 1 0 Write command to 8251
1 X X X No active
 Transmit related
• TxD: Transmitter data pin. Parallel data
received by the CPU are transmitted
serially by this pin.
• TxRDY: Logic 1 means the chip is ready to
accept a new data. After receiving a data, it
is reset.
• TxE: Logic 1 indicates that the serial buffer
in the transmitter is empty.
• TxC: Transmitter clock.
 Receiver related
• Rxd: Receiver data pin. Data is received serially
on this pin and assembled into parallel characters.
• RxRDY: Logic 1 indicates that the USART has
received a data on its serial input "RxD" and is
ready to transfer it to the CPU. It is reset when the
data is read by the CPU.
• RxC: Receiver clock
• SYNDET: Two functions depending on working
mode.
 Programming 8251
• Write to Control port
– Mode word
– Command instruction

• Read from Status port

– Status byte
Mode word
7 6 5 4 3 2 1 0

Asynchronous: Data Length

Parity Baud rate
Number of stop bit 00-5 bits
0-odd 00-syn mode
00-invalid 01-6 bits
1-even 01-x 1 clock
01-1 bit 10-7 bits 10-x 16 clock
10-1.5 bit Parity enable 11-8 bits 11- x 64 clock
11- 2 bit 0-disable
Synchronous: 1-enable
Number of stop bit
00-invalid
01-1 bit
10-1.5 bit
11- 2 bit
 Command instruction

7 6 5 4 3 2 1 0
EH IR RTS ER SBRK RxE DTR TxE

• Bit 0: Transmit enable. Enable transmitter when this bit is set.

• Bit 1: Data terminal ready. Setting this bit will force the DTR output low.
• Bit 2: Receive enable. Enable receiver when this bit is set.
• Bit 3: Send break character. Setting this bit forces TxD low.
• Bit 4: Error reset. Setting this bit clears the PE, OE and FE error flags.
• Bit 5: Request to send. Setting this bit forces the CTS output low.
• Bit 6: Internal reset. Setting this bit will reset 8251 and prepare for a new mode instruction.
• Bit 7: Enter hunt mode. Setting this bit enables a search for SYNC characters.
 Status byte

7 6 5 4 3 2 1 0
DSR SYNDET FE OE PE TxE RxRDY TxRDY

• Bit 7: This bit will go logic 1 whenever DSR is low.

• Bit 6: This bit will go logic 1 when a sync byte is received in synchronous mode.
• Bit 5: Framing error. This bit will go logic 1 when stop bits are not detected.
• Bit 4: Overrun error. This bit will go logic 1 if a new data is received before the
processor read the last one.
• Bit 3: Parity error. This bit will go logic 1 if the parity of the received data is wrong.
• Bit 2: Transmit empty. This bit will go logic 1 if the data bus buffer is empty.
• Bit 1: Receive ready. This bit will go logic 1 if the receiver has received a complete data.
• Bit 0: Transmit ready. This bit will go logic 1 if the transmitter is ready to transmit a
new data.
 I/O flowcharts
Reading Writing
 Program

Data Input: read data from Data Output: Data stored in AL

is output to the transmitter if
receiver, returning it in AL. the transmitter is ready.
CHARIN PROC FAR
CHAROUT PROC FAR
RSTAT: IN AL, 79H ; read status byte
MOV AH, AL ; save the data
AND AL, 02H ;examine RxRDY
TSTAT: IN AL, 79H ; read status byte
JZ RSTAT ; wait until receiver is ready. AND AL, 1 ; examine TxRDY
IN AL, 78H ; read receiver JZ TSTAT ; wait transmitter is ready
RET MOV AL, AH ; get data back
CHARIN ENDP OUT 78H,AL ; output to transmitter
RET
CHAROUT ENDP
 Application: Read Com1
• Address range: 3F8H~3FFH
– Data port: 3F8H
– Status port: 3FDH
• Bit 0: Logic 1 when receiver ready
• Bit 5: Logic 1 when transmitter ready
• READCOM1:
– Read data received by COM1
– Display it on the display screen
. MODEL SMALL
. DATA
XMSG DB ‘Press any key to exit…’ 0DH, 0AH,’$’ ; 0DH=ASCII code of CR, enter
DSTR DB ‘is’
CDATA DB 20H
DB 0DH, 0AH, ‘$’ ; 0AH=ASCII code of LF, change line
.CODE
.STARTUP
LEA DX, XMSG ; set up pointer to exit message
MOV AH, 9 ; display string function
INT 21H ; DOS Call
COM1: MOV DX, 3FDH ; set up status port address
MORE: IN AL, DX ; read UART status
TEST AL, 1 ; has data been received?
JNZ READ ; yes, go get it
AKEY: MOV AH, 0BH ; check keyboard status
INT 21H
CMP AL, 0FFH ;has any key been pressed?
 JNZ MORE
JMP BYE
READ: MOV DX, 3F8H ; set up data port address
IN AL, DX ; read UART receiver
MOV CDATA, AL ; save character
CMP AL, 20H ; test for printable ASCII
JC NONPRT
CMP AL, 80H
JC OKVAL
NONPRT: MOV CDATA, 20H ; use a blank when non-printable
OKVAL: CALL DISPBIN ; display data in binary
LEA DX, DSTR ; setup printer to data string
MOV AH, 9 ; display string function
INT 21H ; DOS CALL
JMP AKEY ; and repeat
BYE: .EXIT
DISPBIN PROC NEAR
MOV CX, 8 ; setup loop counter
NEXT: SHL AL, 1 ; move bit into carry flag
PUSH AX ; save number
JC ITIS1 ; was the LSB a 1?
MOV DL, 30H ; load ‘0’ character
JMP SAY01 ; go display it
ITIS1: MOV DL, 31H ;load ‘1’charcter
SAY01: MOV AH, 2 ; display character function
INT 21H ; DOS CALL
POP AX ; get number back
LOOP NEXT ; repeat
RET
DISPBIN ENDP
END
7.3 8259 Programmable interrupt controller
• Interrupt-processed I/O technique
– Allow the CPU to execute any type of
subroutines
• Interrupt
– Software interrupt
– Hardware interrupt
• INTR: Interrupt request.
• NMI: Non-maskable interrupt.
• INTA: Interrupt acknowledge.
 Software interrupt(Review)
• Set by Programmer in software
• Interrupt vectors table
– Pointed by interrupts
– Address of interrupt entry (CS:IP)
 Interrupt instructions
• Three instructions for programmer:
– INT N
• Software interrupt instruction
– INTO
• Overflow interrupt
– INT 3
• Special software interrupt as interrupt instruction is
1 byte
 INT N
• 0<=N<=256, N*4=vector table address
• Steps:
– Pushes the flags onto the stack
– Clear trace flag and interrupt-enable flag
– Push the current CS register onto the stack
– Fetches the new CS location from the vector table
– Push the current IP onto the stack
– Fetches the new IP location from the vector table
– Jump to this new location
 INTO
• Encountered when overflow happens
(OF=1)
• Vector table address is 0010H
• An INTO appears after every addition and
subtraction
– OF=0, no operation executed.
– OF=1, go interrupt.
 INT 3
• Breakpoint interrupt.
• Interrupt instruction is 1 byte.
• Often used for debug.
– Display the contents of all register
 IRET
• Interrupt return instruction
– Pop stack data back into IP
– Pop stack data back into CS
– Pop stack data back into flags.
• Resume the program interrupted before.
 Hardware Interrupt
• Two hardware interrupt inputs:
– NMI and INTR
• NMI: Non-maskable interrupt
• Internally decoded, type-2 interrupt
• Edge-triggered
– Positive edge (0 1)
– Low remain for at least two clocking periods
• For major system interrupt
• Always causes an interrupt
• INTR: Interrupt request
– Externally decoded, reserved interrupt vector
– Level-sensitive
• hold at logic 1 until recognized by CPU
• Return to logic 0 before the end of interrupt service
procedure
– Enable and disable by Interrupt-enable flag (IF)
• CLI( Clear interrupt-enable flag): Disable INTR
• STI(Set interrupt-enable flag): Enable INTR
• INTA: Put an interrupt type number onto the
data bus in response to the INRT input.
 8259
• Necessity
– Many interrupt-driven I/O exist
– Each device will request interrupts with
individual priorities
• Function
– Handle 8 levels of prioritized interrupts
– Cascadable for up to 64 levels of interrupts
– Reconfigurable at any time
Block diagram
 Block function
INTERRUPT REQUEST REGISTER (IRR)
Stores all the interrupt levels which are requesting
service
IN-SERVICE REGISTER (ISR)
Stores all the interrupt levels which are being serviced.
PRIORITY RESOLVER
Determines the priorities of the bits set in the IRR
INTERRUPT MASK REGISTER (IMR)
Stores the bits which mask the interrupt lines to be
masked
Pin function
Interface of 8259
Flows:
1.Interrupt request is input to IR
input. The corresponding bit in
the IRR is set.
2.8259 examines the request and
issue an INTR signal to CPU and
CPU responds with a pulse on
INTA.
3.8259 sets the bit in the in-service
register and clear the
corresponding bit in the interrupt
request register.
4.CPU outputs a second pulse on
INTA.
5.8259 outputs an 8-bit interrupt
vector number on the data bus.
This number is used to select the
corresponding interrupt service.
 Programming
• Two control words
– Initialization command words (ICW)
• A sequence of 2-4 bytes for initialization.
• ICW1, ICW2, ICW3, ICW4

– Operation command words (OCW)

• A sequence of 3 bytes for handling each interrupt.
• OCW1, OCW2, OCW3
• ICW1
0 0 0 1 LTIM 0 SNGL IC4

– IC4: Logic 1 indicates ICW4 must be read

during initialization.
– SNGL: Logic 1 indicates only one 8259 is used.
0 indicates 8259 could be cascaded.
– LTIM: Logic 1 indicates IR is level-sensitive
and Logic 0 indicates IR is edge-sensitive.
– Bit 4: Flag of ICW1
 Example:
• What’s the interpretation of ICW1 when it
contains IAH?
• 1AH= 00011010B
0 0 0 1 LTIM 0 SNGL IC4

• Level sensitive, one 8259 is used and ICW4 is

not required.
• ICW2
T7 T6 T5 T4 T3 0 0 0
– Program the eight interrupt vector numbers
– T3~T7 five most significant bits of the vector number
– Low 3 bits are generate by IR input.
• IR0--------------0 0 0
• IR1--------------0 0 1
• IR2--------------0 1 0
• IR3--------------0 1 1
• IR4--------------1 0 0
• IR5--------------1 0 1
• IR6--------------1 1 0
• IR7--------------1 1 1
• ICW3
• Only for cascade 8259
– Master
S7 S6 S5 S4 S3 S2 S1 S0
• Indicate which IR is connected
with salve 8259
– Salve
0 0 0 0 0 ID2 ID1 ID0

• Indicate the id of the cascaded

salve 8259
• ICW4
0 0 0 SFNM BUF M/S AEOI 1
– Only needed when IC4 is set.
– AEOI: Automatic end of interrupt
• Logic 1: Clears the selected bit in the in-service register.
• Logic 0: The in-service bit must be cleared manually.
– M/S: Master/Salve
• Logic 1: Master mode
• Logic 0: Salve mode
– BUF:
• Logic 1: Buffer mode.
– SFNM:
• Logic 1: Special fully nested mode, when multiple 8259
cascaded.
 Example
• Write the instructions needed to program a single 8259 to operate as a
master and provide the following features:
1. Edge-sensitive interrupts. 2. ICW4 needed. 3. A base interrupt vector
number of 40H. 4. No special fully nested mode. 5. No buffered mode.
6 . AEOI mode enabled.
• Solution:
– The data value of each ICW
• SNGL=1, IC4=1 and LTIM=0, so ICW1=13H
• Base vector number=40H, so ICW2=40H
• SFNM=0, BUF=0, M/S=0, AEOI=1, so ICW4=03H
– Instructions
• MOV AL, 13H
• OUT F8H, AL ; output ICW1
• MOV AL, 40H
• OUT 0F9H, AL ; output ICW2
• MOV AL, 03H
• OUT 0F9H, AL ; output ICW4
 OCWs
• Be output to 8259 after initialization

• Used to handle each interrupt

• OCW 1:
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

– Used to mask off selected interrupts by setting 1

in corresponding bit.
– Example: What interrupts are disabled by
writing 10100001 into OCW1?
– Answer: IR7, IR5 and IR0.
• OCW2
R SL EOI 0 0 L2 L1 L0

R SL EOI Function
0 0 1 Nonspecific EOI command
0 1 1 Specific EOI command
1 0 1 Rotate on nonspecific EOI command
1 0 0 Rotate in AEOI mode
0 0 0 Rotate in AEOI mode
1 1 1 Rotate on specific EOI command
1 1 0 Set priority command
0 1 0 No operation

• L2, L2 and L0: IR level to be acted upon.

• OCW3
0 ESMM SMM 0 1 P RR RIS

– ESMM: Enable Special Mask Mode

• Logic 1: enable the SMM bit to set or reset
• Logic 0: SMM has no meaning
– SMM: Special Mask mode
• Logic 1: Special mask mode with ESMM=1.
• Logic 0: Normal mask mode with ESMM=1.
– P: Poll
• Logic 1: Don’t generate interrupt request.
– RIS: Read interrupt Status
• The contents of status of 8259
 Review
• Interrupt
– Software interrupt
– Hardware interrupt
• 8259----Programmable Interrupt controller
– Interface
• Pin function
– Programming
• Control words
– ICWs
– OCWs
 7.4 8254 Programmable interval timer

• Programmable interval timer

– Timing with hardware
– Interrupt the processor at the end of timing
• 8254
– Three independent 16-bit counters
– Multiply purposes
• Real-time clocks
• Time delay generator
• Frequency measurement
• Pulse-width modulation
Overview
Pin function
Interface of 8254

Address Port
CC80H Counter 0
CC81H Counter 1
CC82H Counter 2
CC83H Control word
 Programming the 8254
• Writing a Control word
– Control word register
– Specify which counter is being programmed.
• Writing an initial count
– Load in counter
– Determined by the Control word
Control word
 Mode definitions
• Mode 0: Interrupt on terminal count
– Typically used for event counting
– OUT=0 unless Counter reaches zero
– OUT=1 unless a new count or a new Control word
is written
– GATE=1 enables counting
– GATE=0 disable counting
Mode 1: hardware retriggerable one-
shot
• OUT: initially high, will go low on the CLK
pulse following a trigger and will remain
low until the counter reaches zero. Will
then go high and remain high until the CLK
pulse after the next trigger.
 Mode 2: Rate generator
• OUT : initially high, and go low for one CLK
pulse when initial count decrement to 1 and
then go high again. The counter reload the
initial count and the process is repeated.
• GATE=1 enables counting; GATE=0 disables
counting.
 Mode 3: Square wave mode
• Use for baud rate generation.
• OUT initially high and goes low and remains
low after half initial count has expired.
• GATE=1 enables counting; GATE=0 disables
counting.
 Mode 4: Software triggered
strobe
• OUT: initially high and goes low for one CLK
pulse when initial count expires and goes high
again.
• The counting sequence is “triggered” by
writing the initial count.
• GATE=1 enables counting, GATE=0 disables
counting.
 Mode 5: Hardware triggered
strobe
• Counting is triggered by a rising edge of
GATE.
• OUT: initially high and goes low for one
CLK pulse when the initial count has
expired.
Summary

• Output of OUT
• Method for initiating
counting
• Function of GATE
 Example

• MOV DX, 0CC83H

What instructions are • MOV AL, 39H
needed to program counter
• OUT DX,AL ; output control
0 for BCD counting in mode
4? The initial count is 4788. word
Solution: Output the control • MOV DX, 0CC80H
word to port CD83H and the • MOV AL, 88H
initial count to port CC80H.
The control word needed to • OUT DX, AL ; output lower 8
program counter 0 for BCD bits
counting in mode 4 and a 16-
bit initial count is 39H. The
• MOV AL, 47H
initial count is represented by • OUT DX,AL ; output upper 8
the Hex-pairs 47H and 88H. bits
 Assignments
1. Determine the mode words for each 8255
configuration:
(a) Mode 0, A in, B out, C in
(b) Mode 1, A out, B in
2. Show the instruction needed to program the 8251 for:
(a) Asynchronous mode, 7data bits, odd parity, X16 clock, 2
stop bits.
(b) Synchronous mode, 7 data bits per character.
3. What’s the main difference between polled I/O and
interrupt-driven I/O?
4. What instructions are needed to program counter 2 in
an 8254 for binary counting in mode 0? The initial count
is 3000H. Assume the base port address is B0H.