Chip Design Trend &

Fabrication Prospects in India

BY:
Bibhuti Bikramaditya
Technical Leader
DCA Electronic System Design
Pune

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Topics of Discussion
 Chip design in Brief
 Chip design application Areas
 Latest chip design trend
 Fabrication prospect
 conclusion

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Chip design in brief
 Historical journey
 VLSI Techniques
 FPGA Vs. ASICs
 New FPGA Revolution
 Embedded advantages

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Historical Journey
 Just after Invention of Transistors in the end
of 1947 and the beginning of 1948 , valve
era supposed to become obsolete and the
journey of Modern Electronics began.
 Miniaturization of ICs started with the idea of
putting more no. of Transistors into one
silicon chip
 SSI : < 12 Gates.
 MSI: <100 Gates
 LSI : <1000 Gates
 VLSI: < 10000 Gates

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 IC Era (from SSI To VLSI)
IC in 1960’s IC in 2003’s
 Only 2 transistors and one • More than 40 million transistors
resistor. and other components and expected
to be of order of Billions of
transistors by 2005.
 Size of chip was more than
required. • Every part of the chip is utilized.
 Unable to deal with complex • Efficient in dealing with complex
functionalities. functionalities.
 Excess power dissipation.
• Power dissipation brought in
control.
 Speed was not significant.
• Million of operations can be done
in just one second. 5
IC Design Technique from layout level to
system level

The introduction of HDLs have made possible the

design of complete System on Chip(SOC), with the
complexities rising from 1 million to 10 million
transistors.Recently System C has been introduced
for 100 million to 1000 millions of transistors. 6
IC Design Growth at frequency level

The clock frequency increased for high performance

micro processor and industrial micro controllers with
the technology scale down. here motorola micro
controler has been taken as the example
used for high performance automotive industry
applications.
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Intel Microprocessor Growth

Describes the evolution of complexity of

intel@ micro processors in terms of no. of
devices on the chip the pentium 4
processor produced in 2003 is 50 million
MOS devices integrated on a single piece
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of silicon no larger than 2 x 2 c.m.
Evolution of Memory Size

First 1 kb memory produced by Intel in

1971 , semiconductor memory have
advanced both in density as well as
performances. With the production of 256
Mb memories in 2000 and 1Gb in 2004
according to the estimates , it will 9
expected to increase up to 16 Gb in 2008.
Evolution of Lithography

Trend towards the smaller dimension has

been accelerated since 1996. in 2007,
the lithography is expected to decrease
down to 0.07 um .
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Evolution of silicon area for NAND Gate
Fig shows how fabrication for Simple
NAND gate become complex as its
feature size is decreasing almost
exponentially.

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Typical Structure ICs

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Moor’s Law Vs. IC Technology Growth
First Law: Silicon Technology will double the
number of transistors per chip every 18 months !!!
all above example shows its validity.

In other way ,its minimum feature size must

decrease by a factor of 0.7 every three years

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VLSI Techniques
 Stands for Very Large Scale Integration.
This is the technology of Putting millions
of transistors into one silicon chip.
 Tools (for VLSI)
(1) Modelsim 5.5b: Simulation
Simulation is used for the testing the
behavior of outputs on the waveform
according to their input given.
(2) Leonardo Spectrum 3 : Synthesis
Synthesis tool is used for looking the
hardware according to the program
written in their languages like
VHDL/VERILOG.
(3) Xilinx 6.1 ISE Pack: Chip
Downloading
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VLSI Techniques
Evolution Of Programmable Devices

(1) PROM: Programmable ROM

(2) PAL: Programmable Array Logic
(3) PLA: Programmable logic Array.
(4) CPLD: Complex Programmable
Logic Devices.
(5) FPGA: Field Programmable Gate
Arrays.
(6) ASIC : Application Specific ICs.
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PLD Trend

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Xilinx FPGA Architecture

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 CPLD Vs. FPGA

Architecture PLA like Gate array like

Density Low to medium Medium to high
Speed Fast, predictable Application dependent
Interconnect Crossbar Routing
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Power consumption High Medium
ASIC Vs. FPGA

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New FPGA Revolution
All Disadvantages of ASICs
(1) Longer time to market
(2) Complex Design methodology
have been overcome by FPGA
In terms of No. of Transistors per chip ,
FPGA Vendors have increased its
capacity and astounding result is coming
as time pass through.
Inclination Towards FPGA is increasing day
by day.
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New FPGA Revolution

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New FPGA Revolution: SPARTAN 3
Recently Introduced

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New FPGA Price Revolution

Price of 100k gates over time 23

Cost Management through System Integration

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Embedded Advantage
 Complete System Design Possible
 Real time application.
 Low cost Chip
 VLSI Goes on embedded as we
can write program in Linux and
Unix Environment.
 System C developed by Xilinx.

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Chip Design Application Areas
 Networking (PCI,Ethernet,USB)
 DSP & Communication
 Speech Processing &Image
processing
 Tele mobile communication.
 Micro processor & Micro controller
Based System.
 Home appliances

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DSP VLSI & Communication
Trend is now to implement all DSP Function and algorithm into VLSI so as it
could make complete chip being largely used for High speed Multimedia
application, tele-mobile communication and GPS System

DSP Performance and Flexibility: FPGA

Solution

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Conventional DSP Software VS.
FPGA Performance advantage

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Image Processing

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Image Processing : MPEG-4

The Brilliant Engineers of DCA

Electronic System Design is also
working on complete Implementation
Of MPEG-4 using VLSI and
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Embedded Technology
Latest Chip Design Trend
 Auto motive Sector
 Biometric analysis for Security
 Neural network & Artificial
intelligence.
 System On Chip Design with
Virtual Component.
 Bio Chips: Rule Based System
 Neuro Chips.

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Auto motive Electronics Market Overview

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Auto motive Applications

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FPGA Solution for Car Manufacturers

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CAR CUBE : Telematics Platforms from Acuna
& Xilinx

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CAR CUBE : Architectural Description

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Auto motive Sector : Issues and Challenges

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Auto motive Sector : In Vehicle Networking

LAN: Local Area Network,

CAN: Control Area Network 38
Auto motive Sector : MOST Application

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Auto motive networks

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Car Multimedia System

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Security System: Encryption & Decryption
AES Algorithm Implementation

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Security System: Encryption & Decryption
AES Algorithm Implementation

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System On Chip Design : with Virtual
Component
In the recycling age, designing for reuse
sounds like a great idea
but with increasing requirements and chip
sizes,its no easy task.

System On Chip may contain both a system

bus connect and Peripheral bus connect
custom I/O block that provide functions not
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commercially available,may also be included
System On Chip Design : with Virtual
Component

Adv. Of System On Chip:

(1) Increased levels of design reuse.
(2) More effective hardware-software co-design.
(3) Better trade-offs between general-purpose vs. domain-specific
architectures and algorithms.
(4) Greater integration of functionality on-chip (hardware-software,
analog-digital).

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Bio Chips : A medical Revolution
developed to sequence unknown genes and to study gene expression. but
the working principle suggest that they can be used for engineering
application that require parallel processing.
DNA chips are proposed here as the physical substrate to store and
evaluate a set of rules for knowledge based systems.

In DNA chips, each cell uses millions of copies of DNA sequence

called probes. The colors indicate that probes are different between
cells 46
 Bio Chips : Design Steps

Fig(1) Single stranded DNA sequences

Fig2 Nucleotide with pyrimidine
base and Purine base

Simplified Diagram for

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Fig3
Bio Chips : Design Steps

Fig6: plant states are sampled and A/DNA Converter

produce millions of two tagged DNA sequences. Small
dot is quantum dot used to identify helix

Fig4:DNA sequence tagged with the

quantum dots. Here half circle
represent Single stranded DNA Fig7:DNA chip is injected with millions of tagged DNA
Sequence and Small dot is the quantum strands. After Scanning the chip and processing the
dot rules o/p is produced

Fig5:Complementary probes and target bind to

fluorescent DNA helix. In practice , there are
millions of probes per cells ,so millions of targets
are required to produce Fluorescent cell after
hybridization
Fig8: DNA chip can be used to detect faults in the
plant. State variables are sampled ,converted into
DNA target and injected into chip. The green cells48
are
fluorescent probes after being excited with UV light
Look up tables as DNA Chips: Rule Based System
Basically , look up table is derived from the past
experience and it can be used to improve the
performance of the closed loop with an existing
controller (fig 9) .
The rules are stored on the chip and the
evaluation of the complete rule base at each
sampling instant is carried out in parallel using
the hybridization of DNA strands.

fig9

Applications:
(1) To store boolean or fuzzy rules
(2) Rule Based System
(3) Plant Behavior
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 Time Delay Neural Network : Phoneme Recognition
(Speech Recognition)

Fig2:Neuron Unit Schematic Diagram

Fig1: component of Speech Recognition System

Fig3: Error Signal Generator Schematic Diagram Fig4:Synapse Unit Schematic Diagram Used for storage
and updates of weight
Conclusion: Using Small dimension CMOS processes, such as 0.35 um ,a 5 mm by
5 mm chip could include up to 150 neurons, 150 synapses and 150 error signal
generator unit to construct full time delay neural network for phoneme recognition,
using just a Single Chip . This chip could then be interfaced with computer to 50
generate fully generated phoneme recognition system
Neuro Chip : Design Dreams

Recently revolutionary Invention of

Neuro Chip wondered the world : if it
mixed with our nervous system ,it will
control Brain’s nervous system and
then according to the program one can
control on his thinking ability also.
Are you not thinking that designing
dream is also not impossible ?

See my article in “The Times Of

India” Education Times dated
sept,30,03 on “VLSI DSP &
Embedded Systems : Emerging
Careers” 51
FABRICATION PROSPECT

1. Chip Design Productivity

2. Chip Design Forecast
3. World Fab Industry Vs. Indian Fab
Industry
4. Why Fab lab doesn’t exist in India?
5. Challenges before Chip Design &
Fab lab

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Chip Design Productivity

Fig1: Actual No. of Transistors in millions per IC

design. This data illustrates that there is little
correlation between transistors count and
engineering effort
Fig 3: Factors Influencing IC Design Effort

Design Productivity = output produced /labour expended

= output per unit worker hour
Manufacturing productivity = value added/labour expended
= value added per unit worker hour.
= (end product selling price- material cost of the
product) worker hour
= dollars per worker hour

Chip design productivity ≠ transistor /gate per unit engineering effort.

Fig2: Normalized Transistors count Vs.Chip design productivity = chip design complexity/ engineering effort.
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Persons week = complexity per unit engineering hour.
Chip Design Fore cast
1.According to a Gartner forecast: 3 per cent
growth in global semiconductor revenue ,
2003 "after its worst fall ever in 2001."
(2) India's chip design industry :revenues of
Rs 1,500 crore ($ 300 million),
(3) Indian Market Share : not up to the mark
but in three-four years ,it will reach on
standard mark. According to a Monster
India.com report, "The integrated circuit (chip)
design industry is pegged to grow into a multi
million dollar industry in India, thanks to the
US slowdown."
(4) Indian Design Industry: performing well
and going global. large semiconductor
vendors are growing their operations in India.
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World Fabrication Industry Vs. Indian Fabrication
Industry 5. Fab Industry:
(a) Around 50 Fab lab Exist in the world,another 50 in near future
(b) First fab lab by Intel Just open in Taiwan ,first in South Asia.
(c) No Complete VLSI Fab Industry In India,
(d) SCL ,Chandigarh has its own LSI Fab lab.
(e) Proposal : Rs.1500 crore (for Indian Govt)
(f) Recently Two Companies joined forces in Fab Industry like
IBM/siemens for 64 Mb Technology and
IBM, Siemens &Toshiba for 256 Mb Technology.
6.Huge Investment Required for Design and Fab Lab:
According to Mr Girish of Texas Instruments, "It's not feasible for many
small Indian companies to make sustained investments for a long
period of time, which is required for product development (including the
area of chips design/manufacture). I don't think we can do that now.
Also, to get into full-scale manufacturing, the government should also
take some efforts. It has to take a decision to shift manufacturing unit
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to smaller towns instead of concentrating on the metros."
Fab lab does not exist : why?

1. Huge Fabrication lab cost

According to Mr Girish of Texas Instruments, "It's not feasible for many small
Indian companies to make sustained investments for a long period of
time, which is required for product development (including the area of
chips design/manufacture). I don't think we can do that now. Also, to get
into full-scale manufacturing, the government should also take some
efforts. It has to take a decision to shift manufacturing units to smaller
towns instead of concentrating on the metros “.
(2)Design Incompetency, Probably India is not
prepared .
The actual problem is that quality talent with the right skills is becoming
scarce. The skills required are in vertical domains (DSP, telecom etc.)
along with in-depth understanding of chip design challenges like
designing for high speed, low power, small size, handling large
complexities, accounting for deep sub-micron effects like signal integrity.
This is assuming that these engineers come with basic microelectronics
skills including an understanding of semiconductors and design basics
like language-based design methodologies. Exposure to contemporary 56
design tools is also important."
Challenges before Chip Design and
Fab Industry
1. System Level Integration:
According to Mr. S.Surinder Lall , Sr Marketic Manager , Xilinx Inc.
(St.Pitsberg) during my words with him :There is still requirement of
System Engineers who can understand the complete system. The trend
towards coding is to write code in C/C++, Matlab/Java and then
converted into VHDL/VERILOG, is not suitable. Chip Design has a long
walk to travel”.
2. Chip Design Limits : There is Physical Limits to the Chip
Design , reported by New york Times by at Paul Packan, a scientist with
Intel Corp., the world's largest chipmaker, said semiconductor engineers
have not found ways around basic physical limits beyond the generation
of silicon chips that will begin to appear next year. Packan called the
apparent impasse "the most difficult challenge the semiconductor industry
has ever faced."
"These fundamental issues have not previously limited the scaling of
transistors," Packan wrote in the Sept. 24 issue of Science. "There are
currently no known solutions to these problems."
According to Dennis Allison, a Silicon Valley physicist and computer designer

If the miniaturization process for silicon-based transistors is halted, hopes for

continued progress would have to be based on new materials, new
transistor designs and advances like molecular computing, the Times
.
reported This Mystry will be solved ultimately . 57
Conclusion:

Despite all these stiff challenges ,

Chip Design Industry is growing not
wittingly fast and are affecting even
common mass to go nuclear as well
as global . Indian Fabrication
Industry is the biggest challenge
and dream also .
Let us see when this dream comes
true.

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The End

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