Signal Integrity:

Applied Electromagnetics and Professional Practice

CHAPTER 8
DIFFERENTIAL SIGNALING
LECTURE SLIDES BY DR. SAMUEL H. RUSS
UNIVERSITY OF SOUTH ALABAMA
CHAPTER 8 OBJECTIVES

• Explain how differential signaling improves signal integrity

• Calculate Zdiff
• Explain how changes in mutual L and C affect Zdiff
• Terminate cables that carry differential signals
• Simulate differential signals
• Explain effects of common-mode signals and clock jitter on
differential signals
WHAT IS IT AND HOW DOES IT
HELP?
• Up until now – ground plane = return path
• Alternative: Route each signal with a dual, inverted
version
• This serves as a return path, tends to cancel ground bounce,
and receiver can operate off of the difference

• This is called differential signaling

• Many modern standards use it – USB, PCI Express, SATA, etc.
• Runs at high speed over inexpensive cables and connectors
EXAMPLE
+ Spaced closely enough to +
- V1 have capacitive and -
inductive coupling
Receiver
+
- V2 Two lines of identical
length, Z0, and
layout impairments
V1 V2
Voltage
Vcommon = ½(V1 + V2) Vdiff = V1 - V2

Time
INTERPRETING IT…

• Vdiff is what carries the signal

• Vcommon usually does not matter, except…
• If it gets too high (or low) receiver can be upset
• Can cause unwanted radiated emissions
WHAT IS ZDIFF?

• Consider an applied • Net voltage swing

VV…
1 I (V1-V2) is doubled
• Looks like the same
V2 I current
Z  2V  2Z
Z 00 is
• So itdifflooks Ilike
doubled
NORMAL DIFFERENTIAL
TERMINATION
• Simply put a
V1 termination of 2Z0
2Z0 between the two load
V2
ends…
• Works very well
• But what about L and
C?
SIMULATION WITH A LOT OF L
AND C…

V1 and V2

• Works well!
Differential Signal: V2 – V1 • The overshoot doesn’t
matter
WHAT IF LINES GET CLOSER?

• Consider it from the point of view of V1?

• V1 has to charge its own line and combat negative current
from V2 due to capacitive coupling
• More on coupling in chapter 9…
• V1 has to drive harder and source more current
• Zdiff can drop as much as 12%
• Formulas are too approximate to be useful
• If it really matters, use a field solver
WHAT IF GROUND PLANE GETS
FARTHER?
• Coupling from signal to ground gets less, and
becomes negligible
• Eventually the differential pair carries its own return
current
• Reaches this point when conductor-to-ground spacing is
roughly double the conductor-to-conductor spacing

• Not common in circuit boards – but this is how

differential-signal cables work
 SURPRISING EFFECT OF CLOCK
JITTER V V 1 2

Vcommon

• So what if the two signals

are out of sync in time? Vdiff
• Causes pulses in Vcommon…
• First signal switches which V1 V2
causes Vcommon to change
• Only effect on Vdiff is
longer rise time Vcommon
Vdiff
ANOTHER VIEW…

Common-Mode Voltage
(pulse train)

Input
Voltages

Diff. Voltage
RESULTS OF ALL THIS…

• So Vcommon is a train of alternating pulses

• And there is no termination for common mode – the only
resistor lies between the two lines!
• The result is a mess – trains of pulses running up and down
the line
• On a cable can cause a lot of radiated (RF energy) emissions
FOUR WAYS TO HANDLE
COMMON-MODE NOISE
• Eliminate asymmetry and clock skew
• Add back the cable shield
• But it is tough to get shields completely correct
• Add a ferrite bead to the cable
• More in the EMI/EMC chapter, but it makes the cable more
expensive

• Alter the termination strategy to add common-mode

impedance…
MODIFIED TERMINATION

• Add R and C so that V1

each line has its own R1  0.9 Z 0 R1 R2  0.1Z 0
termination to
ground R2
R1 C
• For C, if tr is in ps, C is V2
in pF 5t r 10t r
C 
Z0 Z0
2
EXAMPLE
• Diff pair with Z0 = 100Ω and tr = 800 ps
• R1 = 90Ω; R2 = 10Ω; C = (10*800)/100 = 80pF

Common-Mode
Voltage
• Still has one spike
(not perfect) but
much better
Diff. Voltage