COM3 Latchup Overview

David Orser
IP Summit 2010
Introduction

According to Chester, 130nm is the worst node across the industry for
latchup. In COM2 we had hoped that our epi on highly doped P+
substrate would protect us from latch up concerns. Unfortunately,
COM2 has had many parts fail latch-up over the last couple years. As
a result we will be implementing DRC checks to increase our
robustness against Latch-Up.

LSI Proprietary 2
What is latch up?

• Latch up is caused by an SCR (PNPN) structure with enough current

gain (beta) to generate a self sustaining voltage drive.
• Beta can generally be reduced by increasing the width of the base
regions. (2 and 3)
C5: Cap or NMOS in DNWELL VCC
GND C1: Cap or PMOS

4 1
isolated Pwell
2
3

P+ diffusion The SCR is formed by the VCC connected

N+ diffusion
isolated Pwell of C5 (1); the Nwell/DNW of C5 (2);
Poly VEE connect P-substrate (3) and the GND
DNW N well connected Nwell of the capacitor C1 (4)

LSI Proprietary 3
Example:
DNWELL Inverter next to CPMOSA @ GND
VCC

GND VCC-3.3V
N-

GND

N- N+ P+ P+ N+ P- N+ P+ N-

N+ N-
N- (deep Nwell)
N-

N+ N+ N+ P+ P+ N+ N+ P+
N- N- P- N-

N- (deep Nwell)

LSI Proprietary 4
Naming Conventions
Used to identify the rough voltages on tubs
5V VCC

VN12_VCC

VN30_VCC

VP33 VPOS_33

VP12 VPOS_12

Voltage These ‘relative rails’

GND GND VNEG
can slide up or down
VN12 VNEG_12

VN30 VNEG_30

VP33_VEE

VP12_VEE

-5V VEE VSUB

LSI Confidential 5
Example supply naming setup file

VARIABLE NETS_P3 "VCC"

VARIABLE NETS_P2 "VN12_VCC" "VP33" "VPOS_33"

VARIABLE NETS_P1P5 "VP25“

VARIABLE NETS_P1 "VN30_VCC" "VP12" "VPOS_12“

VARIABLE NETS_0 "GND?" "VNEG“

VARIABLE NETS_N1 "VP33_VEE" "VN12" "VNEG_12“

VARIABLE NETS_N2 "VP12_VEE" "VN30" "VNEG_30“

VARIABLE NETS_N3 "VEE" "VSUB"

LSI Confidential 6
 Main DRC Rule for Latch Up

• Additional rules control distance to

tub contacts within adjacent
NTUBs
• If an NWELL guard is placed
between NTUBs rules become
slightly less strict
– Don’t rely on this, use smart placement of
supply domains

http://imatrix.lsi.com/prdmx2/default.asp?action=
Result&current=Official&type=GPD&name=09GP
D0413

LSI Proprietary 7
Example Layout of a Level Translator
NMOS or PMOSA PMOS

< P+ in Non-supply
NWELL
• Circuits naturally tend (latch concern) NWELL connected

toward safe placement

– High Supply  Top of Cell
+5V +3.3V +5V
– Mid supply
devices/cascodes/etc in the
middle
+5V
– Low Supply  Bottom of Cell
+5V

• Be careful when cells will

be tiled
0V -1.5V

LSI Proprietary 8
Methodology

• Automated Checking via the DRC deck

– Tubs are identified as belonging to specific supply groups
– Minimum distance is a function of the assumed voltages of specific tubs

• Checks:
– Top Level: Supplies will be identified by chip pins and regulator pins
– Cell Level: Strict naming conventions should be adhered as much as
possible. Failure to name pins correctly will result in checks missing errors.

• Cells with multiple supply levels (> 3.3V)

– Treat these cells as critical cells (like noise sensitive or high-speed)
– Good latchup prevention starts with designer device placement!
– If cell will be replicated, make certain arrays of cells won’t generate an error

• Devices not connected to supplies but with strong drive are not
checked and could also latch. Keep your eyes open.

LSI Proprietary 9
Questions?