COMBINATIONAL MOS LOGIC CIRCUITS

Basic Concepts
MOS Logic Circuits With Depletion nMOS Loads
CMOS Logic Circuits
Complex Logic Circuits
nMOS
CMOS
Pseudo-nMOS
CMOS Transmission Gates(Pass Gates)
COMBINATIONAL MOS LOGIC CIRCUITS

Cload  Combined
Parasitic device capacitance in the circuit
Interconnect Capacitance Components
seen by the output node
Important Parameters for Combinational Logic Circuits

1. VTC gives DC Operating performance

: Vth & VOL : Important design Parameter
2. Dynamic Transient response characteristics of the
circuit
3. Silicon area occupied by the circuit
4. Amount of static and dynamic power dissipation.
Depletion nMos Loads :Two I/P NOR Gate
Depletion nMos Loads :Two I/P NOR Gate
• Calculation of VOH :When both input voltages VA
and VB,are lower than the corresponding driver
threshold voltage, the driver transistors are turned
off and conduct no drain current. Consequently the
load device, which operates in the linear region,also
has zero drain current.
• ID,load = K n,load /2 [2|VT,load (VOH)| .(VDD-VOH)-(VDD-VOH)2] = 0
• Solution VOH = VDD.
Depletion nMos Loads :Two I/P NOR Gate

• Calculation Of VOL: Three Different Cases:

(i) VA = VOH VB = VOL
(ii) VA = VOL VB = VOH
(iii) VA = VOH VB = VOH

• For the first two cases, (i) and (ii), the NOR circuit
reduces to a simple nMOS depletion load inverter.
Depletion nMos Loads :Two I/P NOR Gate

• Assuming (VTo,A = VTo,B = VTo )

• Driver-to-load ratio of the corresponding inverter

can be found as follows.
Depletion nMos Loads :Two I/P NOR Gate

• VOL from the Depletion Load Inverter

If the (W/L)A = (W/L)B then

VOL values calculated for case (i) and case (ii) will
be identical.
Depletion nMos Loads :Two I/P NOR Gate

In case (iii), where both driver transistorsare turned on, the

saturated load current is the sum of the two linear-mode
driver currents.

Since the gate voltages of both driver transistors are equal

(VA = VB=VOH)
Depletion nMos Loads :Two I/P NOR Gate
an equivalent driver-to-load ratio for the NOR structure

NOR gate with both of its inputs tied to a logic-high voltage is

replaced with an nMOS depletion-load inverter circuit with the
driver-to-load ratio given by above equation.
The output voltage level in this case is

So VOL for case (iii) is lower than the VOL, values calculated for
case (i) and for case (ii), when only one input is logic-high.
Depletion nMos Loads :Two I/P NOR Gate
Conclusion: Worst-case condition from the static operation
viewpoint, i.e., the highest possible VOL, value, is observed in
case (i) or in (ii). for NOR gates.
Design Strategy : Achieve a certain maximum VOL for the
worst case, i.e., when only one input is high.Thus, we assume
that one input (either VA or VB ) is logic-high and determine the
driver- to-load ratio of the resulting inverter using VOL eqn for
case (i). Then set

When both inputs are logic-high, the output voltage is even

lower than the required maximum VOL ,thus the design
constraint is satisfied.
Generalized n Input NOR Gate
 Generalized n Input NOR Gate
Assuming that the input voltages of all driver transistors are
identical,
Generalized n Input NOR Gate

Load transistor Subject to Body

effect(Substrate Bias effect).

No Body effect in driver transistors .

Depletion nMos Loads :Two I/P NAND Gate

Body effect ??
VOH=VDD
Depletion nMos Loads :Two I/P NAND Gate

Calculation Of VOL:
Consider the NAND2 gate with both of its inputs equal to VOH
Depletion nMos Loads :Two I/P NAND Gate

VGS,A=VGS,B-VDS,B

we may neglect, for simplicity, the substrate-bias effect for

transistor A, and assume V T,A = V T,B = V TO since the source-
to-substrate voltage of A is relatively low.
Depletion nMos Loads :Two I/P NAND Gate

kdriver,A =k driver,B = k driver

Output Voltage VOL equal to the sum of the drain-to-

source voltages of both drivers =VOL1 +VOL2
ID= ID,A= ID,B= (ID,A+ ID,B)/2; Simplify for both input VOH & get

ID =(Kdriver)/4[2 (VGS-VT)VDS-VDS2]
With same gate voltage,2 nMOS series connected
transistor behave like one nMOS transistor with
K =0.5k
Generalized NAND Structure with
Multiple Inputs
Neglecting the substrate-Bias effect, and assuming that the threshold
voltages of all transistors are equal to VTO, the driver current ID, in the
linear region can be derived as
Generalized NAND Structure with
Multiple Inputs

If the series connected transistor are identical, (W/L)1=(W/L)2=

(W/L), the width-to-length ratio of the equivalent transistor
becomes
 CMOS Logic Circuits
(Two–Input NOR) Gate
 CMOS Logic Circuits
(Two–Input NOR) Gate
• Switching threshold voltage Vth
Of the CMOS gate :Important design criterion.
• By definition Output voltage is equal to the input voltage at the
switching threshold.
• VA =VB=VOUT =Vth

• Derive Vth
& Compare with Vth,inv
 CMOS Logic Circuits
(Two–Input NOR) Gate
• If kn= kP and VT,n=|VT,p|,the switching threshold of the CMOS
inverter is equal to

VDD/2
 CMOS Logic Circuits
(Two–Input NAND) Gate
 CMOS Logic Circuits
(Two–Input NAND) Gate
Assume that the device sizes in each block are identical.

(W/L)n,A = (W/L)n,B and (W/L)p,A =(W/L)p,B

The switching threshold for this gate is then found as

= VDD/2; If kn= 4kP and VT,n=|VT,p|

 Complex Logic Circuits
using nMOS Depletion Load
Boolean function realize with nMOS depletion-load complex logic
 Complex Logic Circuits using
nMOS Depletion Load
Simple design principle of the pull-down network:
·OR operations are performed by parallel-connected
drivers.
· AND operations are performed by series-
connected drivers.
· Inversion is provided by the nature of MOS circuit
operation.
If all input variables are logic-high,the equivalent driver (W/L) ratio
of the pull-down network consisting of five nMOS transistors is
 Complex Logic Circuits using nMOS Depletion Load
Various configurations For calculating the logic-low voltage level VOL.

VOL1 > VOL2 > VOL3 > VOL4

Complex Logic Circuits using CMOS Logic gates
 Complex Logic Circuits using CMOS Logic gates

• Each driver transistor in the pull down network is

represented by an edge ,and each node is
represented by a vertex in the pull down graph.
New vertex is created within each confined area in
the pull down graph,and neighboring vertices are
connected by an edges which cross each edge in
the pull down graph only once. This new graph
represents the pull up network.
Pseudo-nMOS implementation
 Pseudo-nMOS implementation

• Advantage: The large area requirements of complex

CMOS gates present a problem in high-density designs,
since two complementary transistors, one nMOS and one
pMOS, are needed for every input. One possible approach
to reduce the number of transistors is to use a single pMOS
transistor, with its gate terminal connected to ground, as the
load device .

• Disadvantage: Nonzero static power dissipation, since the

always-on pMOS load device conducts a steady-state
current when the output voltage is lower than VOL.
 Comparision CMOS/nMOS
depletion load
• For n input  no.of transistors used are 2n
in CMOS logic .
 n+1 in nMOS logic
Area ???
Capacitance ???
Speed ????
CMOS Transmission Gate (Pass
Gates)
 CMOS Transmission Gate (Pass
Gates)
• DC Analysis:

ID= IDS,n + ISD,p

CMOS Transmission Gate (Pass
Gates)
CMOS Transmission Gate (Pass
Gates)
CMOS Transmission Gate (Pass
Gates)
Complementary Pass-transistor Logic
(CPL).
Complementary Pass-transistor
Logic (CPL).
CPL circuit essentially consists of
– complementary inputs
– An nMOS pass transistor logic network to generate
complementary outputs
– CMOS output inverters to restore the output signals.
• Advantage:The elimination of pMOS transistors from
the pass-gate network significantly reduces the
parasitic capacitances associated with each node in the
circuit, thus, the operation speed is typically higher
compared to a full-CMOS counterpart.
• Disadvantage: But the improvement in transient
characteristics comes at a price of increased process
complexity.