SEL 4283 Analog CMOS IC Design Single Stage Amplifiers: Small Signal Model 1

SEL 4283 Analog CMOS IC Design
Single Stage Amplifiers
Small Signal Model 1

Types of Amplifier
Type Gain = Output/Input Ideal Rin Ideal Rout
Voltage Av = vout/vin ∞ 0
Current Ai = iout/iin 0 ∞
Tranconductance Gm = iout/vin ∞ ∞
Transresistance Rm = vout/iin 0 0
 Most CMOS amplifiers are transconductance amplifier

• large input resistance
• fairly large output resistance
 If load resistance is high, CMOS transconductance
amplifier is essentially a voltage amplifier.
Single Stage Amplifiers 6

Characterization of Amp
 Large signal static characterization
• plot of output versus input (transfer curve)
• large signal gain
• output and input swing limits
 Small signal static characterization
• AC gain
• AC input resistance
• AC output resistance
 Small signal dynamic characterization
• bandwidth
• noise When designing amplifier,
• power supply rejection we need to optimize for
some performance
 Large signal dynamic characterization parameters.
• slew rate
• nonlinearity The parameters trade
performance with each
other
Components of CMOS Voltage Amp

MOSFET Single Transistor Amp Configurations
Common Source with

(also called Source Degeneration
source follower)
 Two categories of amplifier
• noninverting
 input and output in phase
 common gate
 common drain
• inverting
 input and output out of phase
 common source
 common source with degeneration

Inverter as Amp
 Inverter circuits
• inverters are also common source amps

Active Load CS Amp
 IV plot

Active Load CS Amp – cont.
 Voltage Transfer Characteristic (VTC)

 Spice code for VTC
* simulation file for 0.25 micron CS amp
vvdd vdd 0 2.5

* dc analysis
vin in 0
.dc vin 0 2.5 0.1
.print dc v(out)
M2 out out vdd vdd CMOSP L=1u W=1u

M1 0 in out 0 CMOSN L=1u W=2u
.include TSMC_SCN025Parameters.txt
*.model CMOSN nmos level=1 VTO=0.43 KP=115u LAMBDA=0.06 GAMMA=0.4 PHI=0.3
*.model CMOSP pmos level=1 VTO=-0.4 KP=30u LAMBDA=0.1 GAMMA=0.4 PHI=0.3
.end

 Large-signal voltage swing
• max output voltage
 vIN = 0
 vOUT(max) = VDD - |VTP|
• min output voltage
 vIN = VDD
 M1 linear, M2 sat
 assume |VTP| = VTN, ignore λ
  1
 N v DSN  vGSN  V T  DSN    P  vGSP  V T 
v 2
 2  2
 v  1
 N vOUT V DD  V T  OUT    P V DD  vOUT  V T 
2
 2  2
 
 
 1 

vOUT (min )  V DD  V T  1  
 P 
 1 
 N 
 Small-signal characteristics
• small-signal model
 assume low-frequency input signal – all capacitors ignored!
• to find voltage gain

 gm1vin + vout/rds1 + gm2vout + vout/rds2 = 0
W ' W
gm1vin + gds1vout + gm2vout + gds2vout = 0 gm  2 K' I D 1   V DS   2 K ID
L L
• voltage gain
vout   g m1 g m1 K
'
N W 1 L2
    
vin g ds1  g ds 2  g m 2 g m2 '
K P L1W 2

• small-signal model for output resistance
• to find output resistance

 vout/rds1 + gm2vout + vout/rds2 = iout
gds1vout + gm2vout + gds2vout = iout
• output resistance
vout 1 1 1
 R out    r ds1 r ds 2 
i out g ds1  g ds 2  g m2 g m2 g m2

 Characteristics
'
vout K N W 1 L2
 '
vin K P L1W 2
• voltage gain is not a function of bias current
 linearity quite good
• gain is a weak function (square root) of transistor sizes
 must change W1/W2 by considerable amount to increase gain

Exercise 3-1
 For CS amp with resistive load
VDD
RL
vOUT
vIN M1
a) prove that voltage gain vout/vin = -gm1(RL||rds1)

b) prove that Rout = RL||rds1
c) in terms of linearity, explain why this amp is worse than active
load CS amp

Exercise 3-2
 For diode-connected pMOS circuit VDD
M2
Rin
1
a) prove that input resistance Rin = r ds 2
g m2
b) rederive the voltage gain equation for the active load CS amp
by replacing M2 with its equivalent resistance
VDD
VDD
M2 RL
vOUT
vOUT
vIN M1
vIN M1

Exercise 3-3
 For active load CS amp TSMC 0.25 μm circuit with
parameters V = 2.5 V DD
VT0 (V) K’ (A/V2)  (V-1) W 2 1m


L2 1m
M2
NMOS 0.43 115 x 10-6 0.06
PMOS -0.4 -30 x 10-6 -0.1
vOUT
vIN M1 W 1 2 m

L1 1m
The circuit is biased with VIN = 0.7 V.
a) calculate gm1
b) repeat for gm2
c) calculate voltage gain
d) calculate rds1
e) calculate rds2
f) calculate Rout

CS Amp with Current Source Load
 IV plot
VDD = 2.5 V
W 2 2 m

L 2 1m
M2
VB = 1.2 V
vOUT
vIN M1 W 2 m
1

L1 1m

CS Amp with Current Source Load – cont.
 VTC
VDD = 2.5 V
W 2 2 m

L 2 1m
M2
VB = 1.2 V
vOUT
vIN M1 W 2 m
1

L1 1m

VDD = 2.5 V
W 2 2m

* simulation file for 0.25 micron CS amp using level 49 model L 2 1m
M2
VB = 1.2 V
vvdd vdd 0 2.5
vOUT
* dc analysis
vin in 0 vIN M1 W 2 m
1

.dc vin 0 2.5 0.01 L1 1m
.print dc v(out)
M2 out vb vdd vdd CMOSP L=1u W=2u

M1 out in 0 0 CMOSN L=1u W=2u
vvb vb 0 1.2
*.model CMOSN nmos level=1 VTO=0.43 KP=115u LAMBDA=0.06 GAMMA=0.4 PHI=0.3
*.model CMOSP pmos level=1 VTO=-0.4 KP=30u LAMBDA=0.1 GAMMA=0.4 PHI=0.3
.end

 Large-signal voltage swing
• max output voltage VDD = 2.5 V
 vIN = 0 W 2 2m

L 2 1m
 M2 always on M2
 vOUT(max) = VDD VB = 1.2 V
• min output voltage vOUT
 vIN = VDD vIN M1 W 2 m

1

L1 1m
 vOUT should be very small
» M1 linear, M2 sat
 assume |VTP| = VTN, ignore λ
  1 v
 1 v DS 1  vGS 1  V T  DS 1    2  v SG 2  V T 
2
 2  2
vOUT cannot
  1
 1 vOUT V DD  V T  OUT    2 V DD V B  V T 
exceed VDD v 2
 2  2
2
vOUT  min   V DD  V T   V DD  V T   V DD V B V T  2
2
1
2
 V DD  V T   V DD  V T  2  V DD V B V T  2
 1
 I DS
g ds    I DS
1   V DS
 gm1vin + vout/rds1 + vout/rds2 = 0
2 K 'N W 1 I D
gvm1out g m+1 gds2vout = 0
vin + gds1vout L1 1 2 K 'N W 1 1
   

vin gaing ds1 g ds 2
• voltage 
1 I D  2 I D 1   2 L1 I D ID
• to find output resistance, set vin = 0

  gm1vin = 0 1 1
 
• output resistance g ds1  g ds 2 I D  1   2 
Rout r ds1 r ds 2

Exercise 3-4
 For CS amp with current source load with TSMC 0.25 μm
parameters VDD = 2.5 V
W 2 2 m
VT0 (V) K’ (A/V2)  (V-1) 
L 2 1m
M2
NMOS 0.43 115 x 10-6 0.06 VB = 1.2 V
PMOS -0.4 -30 x 10-6 -0.1 vOUT
vIN M1 W 2 m
1

L1 1m
The circuit is biased such that the DC voltage for v OUT is 1.3 V.
a) calculate the DC value for input vIN
b) calculate gm1
c) calculate rds1
d) calculate rds2
e) calculate voltage gain
f) calculate Rout

CS Amp with Push-Pull Load
 Digital inverter circuit
 IV plot
VDD = 2.5 V
W 2 2m

L 2 1m
M2
vOUT
vIN M1 W 1 1m

L1 1m

CS Amp with Push-Pull Load – cont.
 VTC
VDD = 2.5 V
W 2 2m

L 2 1m
M2 Level 1 model
vOUT
vIN M1 W 1 1m

L1 1m
Level 49 model

 Spice code for VTC VDD = 2.5 V
W 2 2m
* INVL49 sub-circuit 
L 2 1m
.subckt INVL49 in out vdd M2
M2 out in vdd vdd CMOSP L=1u W=2u
.include TSMC_SCN025Parameters.txt vOUT
.ends INVL49 vIN M1 W 1 1m

L1 1m
* INVL1 sub-circuit
.subckt INVL1 in out vdd
M2 out in vdd vdd CMOSP L=1u W=2u
.model CMOSN nmos level=1 VTO=0.43 KP=115u LAMBDA=0.06 GAMMA=0.4 PHI=0.3
.model CMOSP pmos level=1 VTO=-0.4 KP=30u LAMBDA=0.1 GAMMA=0.4 PHI=0.3
.ends INVL1
xL49 in outL49 vdd INVL49

xL1 in outL1vdd INVL1
vvdd vdd 0 2.5

vin in 0 ports "in out vdd" of INVL1 connected to
.dc vin 0 2.5 0.01 "in outL1vdd" respectively
.print dc v(outL49) v(outL1)
.end

 Large-signal voltage swing VDD = 2.5 V
• max output voltage W 2 2m

L 2 1m
 vIN = 0 M2
 M2 always on
 vOUT(max) = VDD vOUT
• min output voltage vIN M1 W 1 1m


L1 1m
 vIN = VDD
 M2 off
 vOUT(min) = 0


 gm1vin + vout/rds1 + gm2vin + vout/rds2 = 0
gm1vin + gds1vout + gm2vin + gds2vout = 0W 
 K 'N 1  K 'P W 2 
• voltage
vout gaing m1  g m 2 2  L1 L2  1
    
vin g ds1  g ds 2 ID 1   2  ID
  
 
• to find output resistance, set vin = 0

  gm1vin = gm2vin = 0
• output 1 1
Routresistance
 r ds1 r ds 2  
g ds1  g ds 2 I D  1   2 


Exercise 3-5
 For push-pull CS amp with TSMC 0.25 μm parameters
VT0 (V) K’ (A/V2)  (V-1)

NMOS 0.43 115 x 10-6 0.06
PMOS -0.4 -30 x 10-6 -0.1
The circuit is biased such that the DC voltage for v OUT is 1.3
V.
a) calculate the DC value for input vIN VDD = 2.5 V
W 2 2m
b) calculate gm1 
L 2 1m
M2
c) calculate gm2
d) calculate rds1 vOUT
e) calculate rds2 vIN M1 W 1 1m

L1 1m
f) calculate voltage gain
g) calculate Rout
Summary of CS amps
Type AC Voltage Gain Rout
Resistive load -gm1(RL||rds1) RL||rds1
pMOS active load -gm1/gm2 1/gm2
Current source load -gm1/(gds1 + gds2) 1/(gds1 + gds2)
Push-pull -(gm1 + gm2)/(gds1 + gds2) 1/(gds1 + gds2)

Source Follower Amp
 Also known as common drain amp
 IV plot
vIN = 2.5 V
vIN = 2 V
VDD = 2.5 V
W 1 8m

L1 1m
vIN M1
vOUT
RS 10 kΩ

Source Follower Amp – cont.
 VTC
VDD = 2.5 V
W 1 8m

L1 1m
vIN M1
vOUT
RS 10 kΩ

VDD = 2.5 V
* simulation file for TF of source follower W 1 8m


L1 1m
vIN M1
Mn Vdd In Out 0 CMOSN L=1u W=8u
vOUT
RS Out 0 10k
RS 10 kΩ
vIN In 0
vVdd Vdd 0 2.5
* dc analysis
.dc vIN 0 2.5 0.1
.print dc v(Out)
*.model CMOSN nmos level=1 VTO=0.43 KP=115u LAMBDA=0.06 GAMMA=0.4
PHI=0.3
*.model CMOSP pmos level=1 VTO=-0.4 KP=30u LAMBDA=0.1 GAMMA=0.4
PHI=0.3
.end

W 1 8m
 vIN = VDD 
L1 1m
vIN M1
 VT > VT0 due to body effect!
 M1 is sat because VDS > VGS – VT vOUT
» VDD – vOUT > VDD – vOUT – VT RS 10 kΩ
 to find vOUT(max)
vOUT (max)  1
 V DD  vOUT (max)V T  2
RS 2

 for TSMC 0.25 μm tech with KN’ = 115 μA/V2, VT0 = 0.43 V, and
ignoring body effect (VT = VT0)
 vOUT(max) = 1.5 V for the sample circuit
• min output voltage
 vIN = 0
 M1 off
 vOUT(min) = 0
 Small-signal characteristics VDD = 2.5 V
W 1 8m

• small-signal model vIN M1
L1 1m
vOUT
RS 10 kΩ
+ +
vin vgs1 gm1vin rds1 1/(gmbs1+gm1)

gm1vgs1 rds1 gmbs1vbs1 gm1(vin-vout) rds1 gmbs1vout gm1vin rds1
- - (gmbs1+gm1)vout
vout
RS
vout vout vout

RS RS RS
g mbs   g m
 1 
• to find voltage 
gain  
vout  g m1 vin R S r ds1 
 g mbs1  g m1  2 2  F  V SB
 
vout gain 
• voltage 1 
 g m1 g m1 1
 g m1 R S r ds1   1
 g mbs1  g m1  1  g  g g  g 1  
 vin  ds1 mbs1  g m1
m1 mbs1
RS
vgs1
gm1vgs1 rds1 gmbs1vbs1 gm1vout rds1 gmbs1vout 1/gm1 rds1 1/gmbs1
-
iout iout iout

VDD = 2.5 V
vout vout vout W 1 8m

RS RS RS vIN M1
L1 1m
vOUT
RS 10 kΩ
1 1 1 1 1
R out  R S r ds1   
 g ds1  g m1  g mbs1 g m1  g mbs1 1    g m1
g m1 g mbs1 1
RS

 Characteristics
g m1 1 
vout 
  2 2  F  V SB
vin g m1  g mbs1 1  
1
R out 
1    g m1
• gain < 1
• gain not linear
 depends on VOUT since VSB = VOUT
 can be resolved by using current sink to bias the source follower
• small output resistance

Exercise 3-6
 For CD amp with TSMC 0.25 μm parameters VDD = 2.5 V
W 1 8m
VT0 (V) K’ (A/V2) γ (V0.5) |φF| (V) vIN

L1 1m
M1
NMOS 0.43 115 x 10 -6
0.4 0.3
vOUT
RS 10 kΩ
The circuit is biased with VIN = 2 V.

a) calculate VOUT (can ignore  but do not ignore body effect)
b) calculate gm1
c) calculate gmbs1
d) calculate voltage gain
e) calculate Rout (ignore )

CS Amp with Source Degeneration
 IV plot
vIN = 2.5 V
VDD = 2.5 V
RL 1.3 kΩ vIN = 2 V
vOUT
vIN M1 W 1 8m

L1 1m
RS 440 Ω

CS Amp with Source Degeneration – cont.
 VTC
VDD = 2.5 V
RL 1.3 kΩ
vOUT
vIN M1 W 1 8m

L1 1m
RS 440 Ω

VDD = 2.5 V
* simulation file for TF of CS with degeneration

Mn Out In S 0 CMOSN L=1u W=8u RL 1.3 kΩ
RS S 0 440 vOUT
RL Vdd Out 1.3k
vIN M1 W 1 8m
vIN In 0 
L1 1m
vVdd Vdd 0 2.5
RS 440 Ω
* dc analysis
.dc vIN 0 2.5 0.1
.print dc v(Out)
*.include TSMC_SCN025Parameters.txt
.model CMOSN nmos level=1 VTO=0.43 KP=115u LAMBDA=0.06 GAMMA=0.4
PHI=0.3
.model CMOSP pmos level=1 VTO=-0.4 KP=30u LAMBDA=0.1 GAMMA=0.4
PHI=0.3
.end

RL 1.3 kΩ
 vIN = 0
 M1 off vOUT
 vOUT(max) = VDD
vIN M1 W 1 8m
• min output voltage 
L1 1m
 vIN = VDD
 VDS = vOUT – VS RS 440 Ω
 VGS – VT = VDD – VT – VS
 M1 linear if vOUT < VDD – VT
V DD  vOUT (min)
 to find vOUT(min)
V S  RS
 RL
DD  vOUT (min)
V (1)  v (min)  V S 
  1  vOUT (min)  V S  V DD  V S  V T  OUT 
RL  2 
  V  v (min)
  1  vOUT (min)  V S  V DD  V T  S OUT 
 2 
(2)

+ + vout vout
RL RL
vin vgs1
VDD = 2.5 V
gm1vgs1 rds1 gmbs1vbs1 gm1(vin-vs) rds1 gmbs1vs
- -
RL 1.3 kΩ
vOUT
+ + vIN M1 W 1 8m
vs 
RS vs RS L1 1m
- -
RS 440 Ω
vs
 g mbs1 vs  g m1  vin  vs   g ds1  vout  vs 
RS
v
g m1  vin  vs   g ds1  vout  vs   out  g mbs1 vs
RL
voutvoltage gain g m1 R L g m1 R L
• to find  
vin 1   g m1  g mbs1 R S  g ds1  R L  R S  1   g m1  g mbs1 R S
 (1)
VDD = 2.5 V
iout ix iout RL 1.3 kΩ
+ vout vout vOUT

RL RL
vgs1 vIN M1 W 1  8m
gm1vgs1 rds1 gmbs1vbs1 gm1vs rds1 gmbs1vs L1 1m
-
Rx RS 440 Ω
+ +
RS vs RS vs
- -
• to find output resistance, 1st find Rx

vs 
 g m1 v s  g mbs1 vs  g ds1  vout  vs  (1)
RS
 gds1(vout - vs) = gm1vs + gmbs1vs + ix (2)
 Rx = vout/ix = rds1[ 1 + (gm1 + gmbs1 + gds1)RS ] ≈ (gm1 + gmbs1)RSrds1
 g m1  g mbs1 r ds1 R S R L
 R out  R x R L 
 g m1  g mbs1 r ds1 R S  R L
 Characteristics
vout g m1 R L
 VDD
vin 1   g m1  g mbs1 R S
RL
• if we ignore body effect vOUT

vIN M1
 gain ≈ -gm1RL/(1 + gm1RS)
 much more linear, compared to CS amp
 however, gain is smaller gain = -gm1(RL||rds1)
 vOUT(min) also much lower ≈ -gm1RL
• why more linear?
 if vIN ↑, ID ↑, voltage across RS ↑, VGS ↓, causing ID ↓
 ID less sensitive to input changes

Exercise 3-7
 For CS amp with source degeneration and TSMC 0.25
μm parameters V = 2.5 V DD
VT0 (V) K’ (A/V2)  (V-1) RL 1.3 kΩ
NMOS 0.43 115 x 10-6 0.06 vOUT
vIN M1 W 1 8m

L1 1m
RS 440 Ω
The circuit is biased with VIN = 1.5 V.

a) calculate VOUT (can ignore both  and body effect)
b) calculate voltage gain
c) calculate Rout (do not ignore )

SEL 4283 Analog CMOS IC Design Single Stage Amplifiers: Small Signal Model 1

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SEL 4283 Analog CMOS IC Design Single Stage Amplifiers: Small Signal Model 1

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SEL 4283 Analog CMOS IC Design

Single Stage Amplifiers

Small Signal Model 1

 Most CMOS amplifiers are transconductance amplifier

Single Stage Amplifiers 6

Single Stage Amplifiers 8

Common Source with

Single Stage Amplifiers 9

Single Stage Amplifiers 10

Single Stage Amplifiers 11

Single Stage Amplifiers 12

* simulation file for 0.25 micron CS amp

vvdd vdd 0 2.5

M2 out out vdd vdd CMOSP L=1u W=1u

Single Stage Amplifiers 13

• to find voltage gain

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• to find output resistance

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a) prove that voltage gain vout/vin = -gm1(RL||rds1)

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VT0 (V) K’ (A/V2)  (V-1) W 2 1m

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M2 out vb vdd vdd CMOSP L=1u W=2u

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• min output voltage vOUT

 vIN = VDD vIN M1 W 2 m

• to find output resistance, set vin = 0

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xL49 in outL49 vdd INVL49

vvdd vdd 0 2.5

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• min output voltage vIN M1 W 1 1m

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• to find voltage gain

• to find output resistance, set vin = 0

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VT0 (V) K’ (A/V2)  (V-1)

Type AC Voltage Gain Rout

Resistive load -gm1(RL||rds1) RL||rds1

pMOS active load -gm1/gm2 1/gm2

Current source load -gm1/(gds1 + gds2) 1/(gds1 + gds2)

Push-pull -(gm1 + gm2)/(gds1 + gds2) 1/(gds1 + gds2)

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* simulation file for TF of source follower W 1 8m

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vin vgs1 gm1vin rds1 1/(gmbs1+gm1)

vout vout vout

iout iout iout

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The circuit is biased with VIN = 2 V.

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