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Asynchronous Bus
Asynchronous Bus
Bus arbitration.
A device that wishes to use the bus sends a request to the arbiter. When
multiple requests arrive at the same time, the arbiter selects one request and
grants the bus to the corresponding device. For some devices, a delay in
gaining access to the bus may lead to an error. Such devices must be given
high priority. If there is no particular urgency among requests, the arbiter
may grant the bus using a simple round-robin scheme.
8 CENG 222 - Spring 2012-2013 Dr. Yuriy ALYEKSYEYENKOV
Arbitration
A serial interface.
18 CENG 222 - Spring 2012-2013 Dr. Yuriy ALYEKSYEYENKOV
Serial Interface
Thus, a pause would be needed between two characters to give the processor
time to read the input data. With double buffering, the transfer of the second
character can begin as soon as the first character is loaded from the shift
register into the DATAIN register. Thus, provided the processor reads the
contents of DATAIN before the serial transfer of the second character is
completed, the interface can receive a continuous stream of input data over the
serial line. An analogous situation occurs in the output path of the interface.
During serial transmission, the receiver needs to know when to shift each bit
into its input shift register. Since there is no separate line to carry a clock
signal from the transmitter to the receiver, the timing information needed must
be embedded into the transmitted data using an encoding scheme. There are
two basic approaches. The first is known as asynchronous transmission,
because the receiver uses a clock that is not synchronized with the transmitter
clock. In the second approach, the receiver is able to generate a clock that is
synchronized with the transmitter clock. Hence it is called synchronous
transmission.