Design

Design for
for Testability
Testability

Virendra Singh
Indian Institute of Science
Bangalore
virendra@ {computer, ieee}.org

IEP on Digital System Synthesis

at IIT Kanpur (Dec 11-21, 2007)

Dec 21, 2007 DfT@IITK 1

 Definition
Definition
■ Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
■ DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods:
 Scan
 Partial Scan
 Built-in self-test (BIST)
 Boundary scan
■ DFT method for mixed-signal circuits:
 Analog test bus

Dec 21, 2007 DfT@IITK 2

 Ad-Hoc
Ad-Hoc DFT
DFT Methods
Methods
■ Good design practices learnt through experience are used
as guidelines:
 Avoid asynchronous (unclocked) feedback.
 Make flip-flops initializable.
 Avoid redundant gates. Avoid large fanin gates.
 Provide test control for difficult-to-control signals.
 Avoid gated clocks.
 Consider ATE requirements (tristates, etc.)
■ Design reviews conducted by experts or design auditing
tools.
■ Disadvantages of ad-hoc DFT methods:
 Experts and tools not always available.
 Test generation is often manual with no guarantee of high
fault coverage.
 Design iterations may be necessary.

Dec 21, 2007 DfT@IITK 3

 Scan
Scan Design
Design
 Circuit is designed using pre-specified design
rules.
 Test structure (hardware) is added to the
verified design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode.
 Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
 Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing
test.
Dec 21, 2007 DfT@IITK 4
 Scan
Scan Design
Design Rules
Rules

■ Use only clocked D-type of flip-flops for all

state variables.
■ At least one PI pin must be available for test;
more pins, if available, can be used.
■ All clocks must be controlled from PIs.
■ Clocks must not feed data inputs of flip-flops.

Dec 21, 2007 DfT@IITK 5

 Correcting
Correcting a
a Rule
Rule
Violation
Violation
■ All clocks must be controlled from PIs.

Comb.
logic D1 Q

FF Comb.
D2 logic
CK

Comb.
logic
Q
D1
D2 FF Comb.
logic
CK

Dec 21, 2007 DfT@IITK 6

 Scan
Scan Flip-Flop
Flip-Flop (SFF)
(SFF)
D Master latch Slave latch
TC
Logic Q
overhead

MUX
SD Q

CK D flip-flop

CK Master open Slave open

t

TC Normal mode, D selected Scan mode, SD selected

t

Dec 21, 2007 DfT@IITK 7

 Level-Sensitive
Level-Sensitive Scan-
Scan-
Design
Design Flip-Flop
Flip-Flop (LSSD-
(LSSD-
SFF)
SFF) Master latch Slave latch
D
Q

MCK Q

SCK D flip-flop

SD

Normal
MCK

mode
Logic TCK
overhead
TCK MCK

mode
Scan
TCK

SCK t
Dec 21, 2007 DfT@IITK 8
 Adding
Adding Scan
Scan
Structure
Structure
PI PO

Combinational SFF SCANOUT

logic SFF

SFF

TC or TCK Not shown: CK or

MCK/SCK feed all
SCANIN SFFs.
Dec 21, 2007 DfT@IITK 9
 Comb.
Comb. Test
Test Vectors
Vectors

PI I1 I2 O1 O2 PO

Combinational
SCANIN
SCANOUT
TC
logic
Next
Present S1 S2 N1 N2 state
state

Dec 21, 2007 DfT@IITK 10

 Comb.
Comb. Test
Test Vectors
Vectors
Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

PO O1 O2

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops
Dec 21, 2007 DfT@IITK 11
 Testing
Testing Scan
Scan
Register
Register
■ Scan register must be tested prior to application of
scan test sequences.
■ A shift sequence 00110011 . . . of length nsff +4 in
scan mode (TC=0) produces 00, 01, 11 and 10
transitions in all flip-flops and observes the result at
SCANOUT output.
■ Total scan test length: (ncomb + 2) nsff
+ ncomb + 4 clock periods.
■ Example: 2,000 scan flip-flops, 500 comb. vectors,
total scan test length ~ 106 clocks.
■ Multiple scan registers reduce test length.

Dec 21, 2007 DfT@IITK 12

 Multiple
Multiple Scan Scan
Registers
Registers
■ Scan flip-flops can be distributed among
any number of shift registers, each having
a separate scanin and scanout pin.
■ Test sequence length is determined by the
longest scan shift register.
■ Just one test control (TC) pin is essential.
PI/SCANIN PO/
Combinational
M SCANOUT
logic U
SFF X

SFF
SFF

TC

CK
Dec 21, 2007 DfT@IITK 13
 Scan
Scan Overheads
Overheads
■ IO pins: One pin necessary.
■ Area overhead:
 Gate overhead = [4 nsff /(ng+10nsff )] x 100%,
where ng = comb. gates; nff = flip-flops;
Example – ng = 100k gates, nsff = 2k flip-flops,
overhead = 6.7%.
 More accurate estimate must consider scan
wiring and layout area.
■ Performance overhead:
 Multiplexer delay added in combinational
path; approx. two gate-delays.
 Flip-flop output loading due to one additional
fanout; approx. 5-6%.
Dec 21, 2007 DfT@IITK 14
 Hierarchical
Hierarchical Scan
Scan
■ Scan flip-flops are chained within subnetworks
before chaining subnetworks.
■ Advantages:
 Automatic scan insertion in netlist
 Circuit hierarchy preserved – helps in debugging and
design changes
■ Disadvantage: Non-optimum chip layout.

Scanin Scanout
SFF1 SFF4
SFF1 SFF3
Scanin
Scanout
SFF2 SFF3 SFF4 SFF2

Hierarchical netlist Flat layout

Dec 21, 2007 DfT@IITK 15
 Optimum
Optimum Scan
Scan
X
Layout
Layout X’

IO SFF
pad cell

SCANIN
Flip-
flop
cell
Y Y’

TC SCAN
OUT

Routing
channels
Interconnects Active areas: XY and X’Y’

Dec 21, 2007 DfT@IITK 16

 Automated
Automated Scan
Scan
Design
Design Behavior, RTL, and logic
Rule Design and verification
violations
Scan design
rule audits
Gate-level
netlist
Combinational Scan hardware
ATPG insertion
Combinational Scan
vectors netlist
Scan sequence Scan chain order Chip layout: Scan-
and test program chain optimization,
generation timing verification
Design and test
data for
Test program manufacturing Mask data

Dec 21, 2007 DfT@IITK 17

 Timing
Timing and
and Power
Power
■ Small delays in scan path and clock skew can
cause race condition.
■ Large delays in scan path require slower scan
clock.
■ Dynamic multiplexers: Skew between TC and
TC signals can cause momentary shorting of D
and SD inputs.
■ Random signal activity in combinational
circuit during scan can cause excessive
power dissipation.

Dec 21, 2007 DfT@IITK 18

 Partial-Scan
Partial-Scan
Definition
Definition
■ A subset of flip-flops is scanned.
■ Objectives:
 Minimize area overhead and scan sequence
length, yet achieve required fault coverage
 Exclude selected flip-flops from scan:
 Improve performance
 Allow limited scan design rule violations
 Allow automation:
 In scan flip-flop selection
 In test generation
 Shorter scan sequences

Dec 21, 2007 DfT@IITK 19

 Partial-Scan
Partial-Scan
Architecture
Architecture
PI PO

Combinational
circuit

CK1
FF

FF
CK2 SCANOUT
SFF
TC
SFF

SCANIN
Dec 21, 2007 DfT@IITK 20
 History
History of
of Partial-
Partial-
Scan
Scan
■ Scan flip-flop selection from testability measures,
Trischler et al., ITC-80; not too successful.
■ Use of combinational ATPG:
 Agrawal et al., D&T, Apr. 88
 Functional vectors for initial fault coverage
 Scan flip-flops selected by ATPG
 Gupta et al., IEEETC, Apr. 90
 Balanced structure
 Sometimes requires high scan percentage
■ Use of sequential ATPG:
 Cheng and Agrawal, IEEETC, Apr. 90; Kunzmann and
Wunderlich, JETTA, May 90
 Create cycle-free structure for efficient ATPG

Dec 21, 2007 DfT@IITK 21

 Difficulties
Difficulties in
in Seq.
Seq.
ATPG
ATPG
■ Poor initializability.
■ Poor controllability/observability of state variables.
■ Gate count, number of flip-flops, and sequential depth
do not explain the problem.
■ Cycles are mainly responsible for complexity.
■ An ATPG experiment:
Circuit Number of Number of Sequential ATPG Fault
gates flip-flops depth CPU s coverage

TLC 355 21 14* 1,247 89.01%

Chip A 1,112 39 14 269 98.80%

* Maximum number of flip-flops on a PI to PO path

Dec 21, 2007 DfT@IITK 22

 Benchmark
Benchmark Circuits
Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Sequential depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

Dec 21, 2007 DfT@IITK 23

 Cycle-Free
Cycle-Free Example
Example
Circuit

F2

F3
F1
3
Level = 1 F2

2
s - graph
F1 F3
dseq = 3
Level = 1 3

All faults are testable. See Example 8.6.

Dec 21, 2007 DfT@IITK 24

 Relevant
Relevant Results
Results
■ Theorem 8.1: A cycle-free circuit is always
initializable. It is also initializable in the
presence of any non-flip-flop fault.
■ Theorem 8.2: Any non-flip-flop fault in a
cycle-free circuit can be detected by at
most dseq + 1 vectors.
■ ATPG complexity: To determine that a fault
is untestable in a cyclic circuit, an ATPG
program using nine-valued logic may have
to analyze 9Nff time-frames, where Nff is the
number of flip-flops in the circuit.

Dec 21, 2007 DfT@IITK 25

 A
A Partial-Scan
Partial-Scan
Method
Method
■ Select a minimal set of flip-flops for scan
to eliminate all cycles.
■ Alternatively, to keep the overhead low
only long cycles may be eliminated.
■ In some circuits with a large number of
self-loops, all cycles other than self-loops
may be eliminated.

Dec 21, 2007 DfT@IITK 26

 The
The MFVS
MFVS Problem
Problem
■ For a directed graph find a set of vertices with
smallest cardinality such that the deletion of this
vertex-set makes the graph acyclic.
■ The minimum feedback vertex set (MFVS) problem
is NP-complete; practical solutions use heuristics.
■ A secondary objective of minimizing the depth of
acyclic graph is useful.

3 3

L=3
1 2 4 5 6 1 2 4 5 6
L=2
L=1

A 6-flip-flop circuit s-graph

Dec 21, 2007 DfT@IITK 27

 Test
Test Generation
Generation
■ Scan and non-scan flip-flops are controlled from separate
clock PIs:
 Normal mode – Both clocks active
 Scan mode – Only scan clock active
■ Seq. ATPG model:
 Scan flip-flops replaced by PI and PO
 Seq. ATPG program used for test generation
 Scan register test sequence, 001100…, of length nsff + 4
applied in the scan mode
 Each ATPG vector is preceded by a scan-in sequence to
set scan flip-flop states
 A scan-out sequence is added at the end of each vector
sequence
■ Test length = (nATPG + 2) nsff + nATPG + 4 clocks

Dec 21, 2007 DfT@IITK 28

 Partial
Partial Scan
Scan Example
Example
■ Circuit: TLC
■ 355 gates
■ 21 flip-flops
Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq.
flip-flops length CPU s CPU s cov. vectors length

0 4 14 1,247 61 89.01% 805 805

4 2 10 157 11 95.90% 247 1,249

9 1 5 32 4 99.20% 136 1,382

10 1 3 13 4 100.00% 112 1,256

21 0 0 2 2 100.00% 52 1,190

* Cyclic paths ignored

Dec 21, 2007 DfT@IITK 29
 Flip-flop
Flip-flop for for Partial
Partial
■
Scan
Scan
Normal scan flip-flop (SFF) with multiplexer of the LSSD
flip-flop is used.
■ Scan flip-flops require a separate clock control:
 Either use a separate clock pin
 Or use an alternative design for a single clock pin

D
Master Slave
MUX latch latch Q
SD
TC
CK SFF
(Scan flip-flop)

TC

CK
Normal mode Scan mode
Dec 21, 2007 DfT@IITK 30
 Random-Access
Random-Access Scan
Scan
(RAS)
(RAS)
PI PO
Combinational
logic
RAM

nff
CK
TC bits
SCANIN SCANOUT
SEL
Address decoder

ADDRESS Address scan

register
ACK
log2 nff bits
Dec 21, 2007 DfT@IITK 31
 RAS
RAS Flip-Flop
Flip-Flop (RAM
(RAM
Cell)
Cell)
D Q
From comb. logic To comb.
SD logic
SCANIN Scan flip-flop
(SFF)

CK
TC

SCANOUT
SEL

Dec 21, 2007 DfT@IITK 32

 RAS
RAS Applications
Applications
■ Logic test:
 Reduced test length
 Reduced scan power
■ Delay test: Easy to generate single-input-change
(SIC) delay tests.
■ Advantage: RAS may be suitable for certain
architecture, e.g., where memory is implemented
as a RAM block.
■ Disadvantages:
 Not suitable for random logic architecture
 High overhead – gates added to SFF, address
decoder, address register, extra pins and routing

Dec 21, 2007 DfT@IITK 33

 Scan-Hold
Scan-Hold Flip-Flop
Flip-Flop
(SHFF)
(SHFF) To SD of
next SHFF
D
Q
SD
SFF
TC
Q
CK

HOLD

■ The control input HOLD keeps the output steady at

previous state of flip-flop.
■ Applications:
 Reduce power dissipation during scan
 Isolate asynchronous parts during scan test
 Delay testing

Dec 21, 2007 DfT@IITK 34

 Delay
Delay Test
Test Definition
Definition
■ A circuit that passes delay test must produce
correct outputs when inputs are applied and
outputs observed with specified timing.
■ For a combinational or synchronous sequential
circuit, delay test verifies the limits of delay in
combinational logic.
■ Delay test problem for asynchronous circuits is
complex and not well understood.

Dec 21, 2007 DfT@IITK 35

 Digital
Digital Circuit
Circuit Timing
Timing
Input Output Transient
Signal region
Observation
changes instant

Inputs
Comb.
logic

Synchronized Outputs
With clock
time
Clock period
Dec 21, 2007 DfT@IITK 36
 Circuit
Circuit Delays
Delays
■ Switching or inertial delay is the interval between input change
and output change of a gate:
 Depends on input capacitance, device (transistor)
characteristics and output capacitance of gate.
 Also depends on input rise or fall times and states of other
inputs (second-order effects).
 Approximation: fixed rise and fall delays (or min-max delay
range, or single fixed delay) for gate output.
■ Propagation or interconnect delay is the time a transition takes
to travel between gates:
 Depends on transmission line effects (distributed R, L, C
parameters, length and loading) of routing paths.
 Approximation: modeled as lumped delays for gate inputs.
■ See Section 5.3.5 for timing models.

Dec 21, 2007 DfT@IITK 37

 Event
Event Propagation Propagation
Delays
Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1

1 3
0 1

2 4 6
P2 1

0 2 3
P3

0 2 5

Dec 21, 2007 DfT@IITK 38

 Circuit
Circuit Outputs
Outputs
■ Each path can potentially produce one signal
transition at the output.
■ The location of an output transition in time is
determined by the delay of the path.

Clock period
Final value

Initial value

Fast transitions Slow transitions

time

Initial value Final value

Dec 21, 2007 DfT@IITK 39

 Singly-Testable
Singly-Testable
Paths
Paths
■
(Non-Robust
(Non-Robust Test)
Test)
The delay of a target path is tested if the test propagates a transition via
path to a path destination.
■ Delay test is a combinational vector-pair, V1,V2, that:
 Produces a transition at path input.
 Produces static sensitization -- All off-path inputs assume non-
controlling states in V2.
don’t
care
V1 V2 Off-path inputs
V1 V2

Target
path

Static sensitization guarantees a test when the target path is the only faulty path.
The test is, therefore, called non-robust. It is a test with minimal restriction. A path
with no such test is a false path.
Dec 21, 2007 DfT@IITK 40
 Robust
Robust Test
Test
Conditions
Conditions
■ Real events on target path.
■ Controlling events via target path.
V1 V2 V1 V2
V1 V2
V1 V2 U0
U1
U0
U1
U0/F0 U0/F0
U1/R1 U1/R1

V1 V2 V1 V2
S1 S0
S1 S0
U0/F0 U0/F0 U1/R1 U1/R1

Dec 21, 2007 DfT@IITK 41

 A
A Five-Valued
Five-Valued
Algebra
Algebra
■ Signal States: S0, U0 (F0), S1, U1 (R1), XX.
■ On-path signals: F0 and R1.
■ Off-path signals: F0=U0 and R1=U1.
Input 1 Input 1
AND S0 U0 S1 U1 XX OR S0 U0 S1 U1 XX

S0 S0 S0 S0 S0 S0 S0 S0 U0 S1 U1 XX
U0 S0 U0 U0 U0 U0 U0 U0 U0 S1 U1 XX
Input 2

Input 2
S1 S0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1
U1 S0 U0 U1 U1 XX U1 U1 U1 S1 U1 U1
XX S0 U0 XX XX XX XX XX XX S1 U1 XX

Input
NOT S0 U0 S1 U1 XX Ref.:
Lin-Reddy
S1 U1 S0 U0 XX IEEETCAD-87
Dec 21, 2007 DfT@IITK 42
 Robust
Robust Test Test
Generation
Generation
Test for ↓ P3 – falling transition through path P3: Steps A through E
E. Set input of AND gate to
S0 to justify S0 at output
XX S0 S0
U0 D. Change off-path input
C. F0 interpreted as U0;
to S0 to Propagate R1
propagates through U0
through OR gate
AND gate

A. Place F0 at R1
path origin
Path P3
F0

XX F0 R1
U0 Robust Test:
B. Propagate F0 through OR gate; S0, F0, U0
also propagates as R1 through
NOT gate

Dec 21, 2007 DfT@IITK 43