Adders

Basic Adders
Adders are important in
computers
other types of digital systems in which numerical data
are processed
We must know about adders.
The Half-Adder
Basic rule for binary addition.

The operations are performed by a logic ckt called

a half-adder.
The Half-Adder
The half-adder
accepts two binary
digits on its inputs
and produces two
binary digits on its
outputs, a sum bit
and a carry bit.
The Full-Adder
The full-adder
accepts two input
bits and an input
carry and generates a
sum output and an
output carry.
DECODER
A decoder is a combinational logic circuit that
activates one of several output lines based on the
input code (typically or BCD).

 Two case of decoder

Active-HIGH inputs and outputs.
 Active-LOW inputs and outputs.
2 to 4 Decoder (Active High)

Figure 1: 2 x 4 decoder with active-HIGH inputs and outputs

2 to 4 Decoder (Active Low)
Figure 3 shows a block diagram and a truth table for
a 2 x 4 decoder with active-LOW outputs.
2 to 4 Decoder (Active High)
A combinational logic function that is expressed as a
sum of minterms, therefore, can be implemented by
summing decoder outputs. For example, if f(A,B) =
Σ(0, 2, 3) then f (A,B)= D0 + D2 + D3 so f can be
implemented by the circuit shown in Figure 2

Question: Obtain Boolean expression for the function f, and simplify it.
2 to 4 Decoder (Active Low)
A combinational logic function that is expressed as a
product of maxterms, therefore, can be implemented
by ANDing decoder outputs. For example, if f(A,B) =
П(0, 1, 3) then f (A,B)= D0 x D1 xD3 so f can be
implemented by the circuit shown in Figure 4.
Example
Example

E=enable
BCD to 7 segment Decoder
One decoder of special interest is a BCD-to-7-
segment decoder. Its purpose is to decode BCD
inputs (the binary codes corresponding to the
decimal values 0 - 9) in order to light the appropriate
segments on a 7- segment display. The decoder,
therefore, will need 7 outputs in order to control the
7 segments, which are labeled a through g. Diagrams
of the decoder and a 7-segment display are shown
below.
The decoder should function as follows:
if ABCD = 0000, the display should light the digit 0 (segments a, b, c, d, e, f)
if ABCD = 0001, the display should light the digit 1 (segments b, c)
if ABCD = 0010, the display should light the digit 2 (segments a, b, d, e, g)
.
.
.
if ABCD = 1001, the display should light the digit 9 (segments a, b, c, f, g)
Note that inputs ABCD = 1010 to ABCD = 1111 correspond to
illegal inputs. The designer may wish to treat these inputs as
“don’t cares” or perhaps generate a blank display or special
unique symbols. If the illegal inputs are treated as “don’t
cares”, the truth table would look as follows:
Example
Implement the function below using a 3:8 decoder.
F = (A’B’) + (A’BC) + AB’C’ *Find truth table of the
Boolean Expression
Example
Encoders
Encoders
An encoder is a combinational logic ckt that
essentially performs a “reverse” decoder function.
An encoder accepts an active level on one of its
inputs representing a digit, such as a decimal or octal
digit, and converts it to a coded output such as BCD
or binary.
Encoders can also be devised to encode various
symbols and alphabetic characters.
The Decimal-to-BCD (Binary
Coded Decimal) Encoder
It has 10 inputs
and 4 outputs
corresponding to
the BCD code.
A3 = 8+9
A2 = 4+5+6+7
A1 = 2+3+6+7
A0 = 1+3+5+7+9
 A3 = 8+9
A2 = 4+5+6+7
A1 = 2+3+6+7
A0 = 1+3+5+7+9

NOTE: A 0-digit input is not needed because the

BCD outputs are all LOW when there are no HIGH
input.
 Multiplexer
A multiplexer, or data selector, can also be used to implement combinational
logic circuits. A multiplexer implementation table is used to
determine the input connections for the multiplexer.
A 2 x 1 multiplexer can be used to implement a function of 2 variables, such as
f(A,B)
A 4 x 1 multiplexer can be used to implement a function of 3 variables, such as
f(A,B,C)
A 8 x 1 multiplexer can be used to implement a function of 4 variables, such as
f(A,B,C,D)
Procedure:
1) Draw the truth table
2) Determine which inputs will be connected to the
select lines (note which is the MSB)
3) Express the output F in terms of the other input.
4) Draw the MUX logic diagram.
Example
Implement the function f(A,B,C) = Σ(0, 3, 6, 7) using
a 4 x 1 multiplexer with selection inputs A and B.
Solution:
Example
Implement the function f(A,B,C) = Σ(0, 3, 6, 7) using
a 4 x 1 multiplexer with selection inputs A and B.
Solution:
Circuit Implementation
Demultiplexer
The action or operation of a demultiplexer is
opposite to that of the multiplexer. As inverse to the
MUX , demux is a one-to-many circuit. With the use
of a demultiplexer , the binary data can be bypassed
to one of its many output data lines.
A demultiplexer is a combinational logic circuit that
receives the information on a single input and
transmits the same information over one of 2n
possible output lines.
Demultiplexers are also called as data distributors, since they
transmit the same data which is received at the input to different
destinations.
1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), two
selection lines (S1 and S0) and four outputs (Y0 to Y3). The
input data goes to any one of the four outputs at a given
time for a particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer
which means that two select lines and 4 output lines. The
block diagram of 1:4 DEMUX is shown below.