HDL/PLI Test Toolbox

East-West 2009

Nastaran Nemati
Majid Namaki Shoushtari

Prof. Zainalabedin Navabi

Advanced Topics in Software Engineering 1
University
Springof Tehran
2006
 Contents
 Motivations
 PLI Test Package
 Features of the Test Package
 Fault Injection
 Fault Collapsing
 Fault Simulation
 DFT Evaluation
 Other Applications
 Experimental results
 Summary and Conclusions

2
Motivations :Why HDL Test?
 Design methods are going to higher levels of
abstraction
 Digital system test stays at the gate level

 It must get advanced to RT level

3
Motivations :Why HDL Test?

 Gap between Design and Test Engineers

 Results:
– More test time
– More test effort
– Less testable designs

4
Motivations : Why HDL Test?
 The most important RT level tools are those that
are based on VHDL and Verilog
 Developing test methods compatible with such
hardware description languages
 Benefits: Having both design and its testbench in
an uniform environment

5
Motivations : HDL Limitations
 The overhead of test methods on simulation speed
 Inaccessibility of HDL internal data structure

 Solution: PLI

6
What is PLI?
 Procedural Language Interface
 A library of C language functions
 Accessible to the compiled Verilog data
structure
 Enables the test engineer to explore the
design modules, ports, nets, etc., easily

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PLI Test Package Flow

PLI Function

Test Program

8
Features of Test Package
 Fault Injection
 Fault Collapsing
 Fault Simulation
 DFT Evaluation
 Other Applications
– DFT reconfiguration

9
Fault Injection
 Stuck@Fault
 Transient fault
 Bridging fault
 Coupling fault

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Stuck@ Fault

accForceValue
accReleaseValue

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Stuck at Fault Injection and
Removal
 Just write the value of fault wherever desired
 Simply using access functions

 $InjectFault(wireName, stuck@val);
 $RemoveFault(wireName);

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Transient Fault Injection
 Delay setting is possible
► Transient fault injection

 $TransientFault(wireName, FaultValue, faultDuration)

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Bridging Fault Injection
$BridgingFault(line1, line2, “and”);

$BridgingFault(line1, line2, “or”);

$RemoveBridgingFault(line1,
acc_vcl_add (variable_object, consumer_routine) line2);
acc_vcl_delete (variable_object)

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Coupling Fault Injection

$CouplingFault(FF1, FF2);

$RemoveCouplingFault(FF1, FF2);

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Fault Collapsing

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Serial Fault Simulation
$faultCollapsing

$InjectFault(wireName, faultValue)

$RemoveFault(wireName)
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Parametric DFT and DFT Evaluation

 Parametric DFTs
 Scan evaluation
 BIST evaluation

18
Summary
 A convenient and easy to use environment for test applications in
Verilog HDL using PLI is presented.
 Develop test applications while having the flexibility of any desired
combination of available methods.
 Evaluate DFT in an virtual tester and use this evaluation to design
optimized test programs.
Access routines of PLI makes the development of test methods, easier
and with no mingling in the original design core.
 The results of PLI fault simulator are close enough to those the stand-
alone test application programs.
 Providing test methods in PLI, test designers can benefit from both
HDL test and high speed software test.
 Using the applications and utilities of this test toolbox is very simple
and effortless.

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 References
1. C. J. Hesscot, D. C. Ness, and D. J. Lilja, “A Methodology for Stochastic Fault Simulation
in VLSI Processor Architectures,” In MoBs, 2005.
2. IEEE Std 1364 – 2001, clause 20 through clause 25
3. M. Nadjarbashi, Z. Navabi and M. R. Movahedin, “Line Oriented Structural
Equivalence Fault Collapsing,” in IEEE Workshop on Model and Test, 2000.
4. N. Farajipour, S. B. Hosseini and Z. Navabi, “Utilizing HDL Simulation Engines for
Accelerating Design and Test Processes,” In IEEE Int. East-West Design and Test
Symposium , 2008.
5. P. A. Riahi, Z. Navabi, and F. Lombardi, “Simulating Faults of Combinational IP Core-
based SOCs in a PLI Environment,” DFT, 2005.
6. Z. Navabi, “VHDL: Modular Design and Synthesis of Cores and Systems,” McGraw Hill,
1998.
7. Z. Navabi, S. Mirkhani, M. Lavasani, and F. Lombardi, “Using RT-Level Component
Descriptions for Single Stuck-at Hierarchical Fault Simulation,” Journal of Testing:
Theory and Applications (JETTA), Vol. 20, No. 6, December 2004.
8. M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory
& Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000, pp. 256-257.
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Thanks
Thanks For
For Listening
Listening

Questions?
Advanced Topics in Software Engineering 21
Spring 2006