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Designing of 4 Bit Asynchronous Up Counter Using JK Flip-Flop

Group Number : 05

VLSI CIRCUIT DESIGN [F]


Course Instructor: NIRJHOR TAHMIDUR ROUF
Lecturer,
American International University-Bangladesh
Group Member
Serial No Name ID

01 Md. Rakib Hasan 17-35078-2

02 Bhuiyan, Md. Risalat 17-35182-2

03 Md. Rifat khan 17-34556-2

MD. Jawad-Al-Mursalin
04 17-34703-2
Hoque

05 Md. Shahriar Kabir Supto 17-34672-2


Content
Introduction
Block Diagram
Operation Principle
Implementation
Results
Application
Conclusion
Introduction
A counter is a device which can count any particular event on the basis
of how many times the particular event(s) is occurred. In a digital logic
system or computers, this counter can count and store the number of
time any particular event or process have occurred, depending on a
clock signal. The outputs represent binary or binary coded decimal
numbers. Each clock pulse either increase the number or decrease the
number.
Flip Flop
A flip flop is an electronic circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. It is the
basic storage element in sequential logic.
JK Flip Flop
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only
difference is that the intermediate state is more refined and precise  than that of  a
S-R flip flop.
JK Flip Flop (cont.)

The behavior of  inputs J and K is same as the S and R inputs of the S-R
flip flop. The letter J stands for SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to
the complement state. So, for a value of Q = 1, it switches to Q=0 and
for a value of Q = 0, it switches to Q=1.
Master-Slave JK Flip Flop
JK flip flop suffers from timing problems called “race” , when the output
changes state before the timing pulse of the clock input has time to go
“OFF”. To avoid this the timing problem developed Master-Slave JK Flip-
flop.
Master-Slave JK Flip Flop (cont.)
• The master-slave flip-flop eliminates all the timing problems by
using two SR flip-flops connected together in a series configuration.
• One flip-flop acts as the “Master” circuit, which triggers on the
leading edge of the clock pulse while the other acts as the “Slave”
circuit, which triggers on the falling edge of the clock pulse.
• This results in the two sections, the master section and the slave
section being enabled during opposite half-cycles of the clock signal.
Block Diagram
4-bit up counter Sequence
Operation Principle
• J-k flip flop both input connected with HIGH to always be in the toggle
mode. The output of each flip flop served as binary bits of the final.
So, four flip flop needed for 4-bit counter.
• Four flip flop connected such a way that each flip flop toggling
frequency decreased by two. Since flip flop frequency decrease by
using toggling mode and cascade every flip flop output as clock input
next flip flop get 4-bit counter. All flip flop clock frequency is not same
that’s why it is called asynchronous.
Implementation
Results
Results (cont.)
Application
• Asynchronous counters are used as frequency dividers, as divide by
“N” counters.
• Asynchronous counters are used for low noise emission and low
power applications
• Asynchronous counters are used in designing asynchronous decade
counter.
• It is also used in Ring counter and Johnson counter.
• Asynchronous counters are used in Mod N ripple counters. i.e. Mod 3,
Mod 4, Mod 8, Mod 14, Mod 10 etc.
Conclusion

• From this project we learned & experienced with many things. We


learned the operation of master-slave flip-flop & how to design
asynchronous up counter by using master-slave flip-flop. Overall our
design is successfully done & the simulation is working properly.
THANK YOU