CSE332 / EEE336

Computer Organization & Architecture

MIPS Datapath and its Control
Lecture 7

Rashadul Kabir
North South University
Summer 2020
Outline of this Lecture
 Prelude
 Basic MIPS Implementation
 Logic Design Conventions
 Building a datapath
 Datapath for memory and R-type instructions
 Core MIPS architecture
 The ALU Control
 Designing the ALU Control Unit
 Operation of the Datapath
 Finalizing the Main Control Unit
 Problems with single-cycle implementation

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Prelude

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MIPS Registers left out
 $fp ($30) -> Frame Pointer

4
MIPS Registers left out
 $gp ($28) -> Global pointer

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MIPS Registers left out
 $k0 and $k1 ($26 and $27)
 Reserved by Operating System.
 In case of exception handling, the interrupt handler can use
these registers to save variables inside a program it interrupts.

 $at($1)
 Reserved for Assembler to interpret pseudo-instructions.
 For example, ‘blt’ instruction is converted into ‘slt’ and ‘bne’
instructions.

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7
Basic MIPS Implementation
 We're ready to look at an implementation of the MIPS
instruction set.
 Simplified to contain only
 arithmetic-logic instructions: add, sub, and, or, slt
 memory-reference instructions: lw, sw
 control-flow instructions: beq, j
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format

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An abstract view of the implementation of the MIPS
subset

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… including necessary multiplexers and control
lines

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Logic Design Conventions
 The datapath elements in the MIPS implementation consist
of two different types of logic elements.
 Elements that operate on data are called combinational

elements.
 Elements that contain data are called state or sequential

elements.
 Combinational logic reads input data from one register and
writes output data to another, or same, register.

Combinational logic hardware units

State State
element Combinational logic element
1 2
State
Combinational logic
element

Clock cycle

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State Elements
 State elements contain data in internal storage, e.g.,
registers and memory.
 Flip-flops and latches are 1-bit state elements, equivalently,
they are 1-bit memories.
 The output(s) of a flip-flop or latch always depends on the
bit value stored, i.e., its state, and can be called 1/0 or
high/low or true/false.
 The input to a flip-flop or latch can change its state
depending on whether it is clocked or not.

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Building a Datapath
 A portion of the datapath used for fetching instructions and
incrementing the program counter:

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Elements needed for R-format ALU operations

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Additional Elements for load/store

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Datapath for a branch instruction

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Datapath for memory and R-type instructions

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Core MIPS architecture combines the elements required by different
instruction classes

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The ALU Control
 The MIPS ALU defines the 6 following combinations of four
inputs.

ALUOp generation
by main control
2
4
ALUOp To
Main ALU
ALU ALU
Control Control
control
input

Instruction
funct field
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Something to remember!

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Designing the ALU Control Unit

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Datapath with necessary control lines
identified

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Effect of the seven control signals

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Operation of the Datapath

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Setting of control lines is determined by opcode
fields

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R-Type Instruction

ADD
0
M
ADD
ADD U
4 rs rt rd X

I[25:21] I[20:16] I[15:11] 1

PC <<2 PCSrc
Instruction
ADDR RD I
32
0
5
1
0
Instruction Value depends on
Memory
MUX RegDst ????
Operation funct
16

RN1
5 5

RN2 WN
5
1 4
3

RD1
Register File ALU Zero
0
WD 0
immediate/
offset RD2
M MemWrite 0
MemtoReg
U ADDR
I[15:0] RegWrite X 1
1
Data
E Memory RD M
U
1 16 X
T
32 ALUSrc
WD X

Control signals
N
D
0 MemRead 0

shown in blue 0

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lw Instruction

ADD
0
M
ADD
ADD U
4 rs rt rd X

I[25:21] I[20:16] I[15:11] 1

PC Instruction
<<2 PCSrc
ADDR RD I
32
0
5
1
0
Instruction
Memory
MUX 0010
RegDst Operation
16 5 5 5
0 43
RN1 RN2 WN
RD1
Register File ALU Zero 0
WD 0
immediate/
offset RD2
M MemWrite 1
MemtoReg
I[15:0]
U ADDR
RegWrite X
1
1
Data
E Memory RD M
U
1 16 X
T
32 ALUSrc
WD X

Control signals
N
D 1 MemRead 0

shown in blue 1

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sw Instruction

ADD
0
M
ADD
ADD U
4 rs rt rd X

I[25:21] I[20:16] I[15:11] 1

PC Instruction
<<2 PCSrc
ADDR RD I
32 5 0
Instruction 0
MUX
1
0010
RegDst Operation
Memory 16 5 5 5
X 4
3
RN1 RN2 WN

Register File
RD1
ALU Zero 1
WD 0
immediate/
offset M MemWrite X
MemtoReg
RD2 U ADDR
I[15:0] RegWrite X
1
1
Data
E Memory RD M

0
U
16 X 32 ALUSrc X
T WD

Control signals
N
D 1 MemRead 0

shown in blue 0

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beq Instruction

ADD
0
M
ADD
ADD U
4 rs rt rd X

I[25:21] I[20:16] I[15:11] 1

PC <<2 PCSrc
Instruction
ADDR RD I 5
1 if Zero=1
32
Instruction
Memory
0
MUX
1
0110
RegDst Operation
16 5 5 5
X 4
3
RN1 RN2 WN

Register File
RD1
ALU Zero 0
WD 0
immediate/
offset M MemWrite X
MemtoReg
RD2 U ADDR
I[15:0] RegWrite X 1
1
Data
E Memory RD M

0
U
16 X 32 ALUSrc X
T WD

Control signals
N
D
0 MemRead 0

shown in blue 0

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Finalizing the Main Control Unit
Inputs
Op5
Op4
Op3
Op2
Op1
Op0

Outputs
R-format Iw sw beq
RegDst

ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1

ALUOpO

Main control PLA (programmable

logic array): principle underlying
PLAs is that any logical expression
can be written as a sum-of-products

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Problems with single-cycle implementation
 Assuming fixed-period clock, and for every instruction
datapath uses one clock cycle implies:
 CPI = 1
 Cycle time is determined by length of the longest instruction path
(load)
 But several instructions could run in a shorter clock cycle: waste of time
 Consider if we have more complicated instructions like floating point!
 Resources used more than once in the same cycle need to be
duplicated
 Waste of hardware and chip area

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Suggested reading
Sections 2.8, 2.12, 4.1, 4.2, 4.3 and 4.4, Computer
Organization and Design (Fifth Edition) - D. A. Patterson and
J. L. Hennesey

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Thank you!

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