A focused mind is one of the most

powerful forces in the Universe.

-Swami Vivekananda
 Chapter 3

Input / Output
Organization
 Chapter objectives
• Program-controlled I/O using polling
• Interrupts
• DMA
• Data transfer over synchronous and
asynchronous buses
• Commercial bus standards, PCI, SCSI, USB
 Input / Output

• Communication
• Exchange information
 Accessing I/O devices
• Single-bus structure
• Memory-mapped I/O

Move DATAIN, R0
Move R0, DATAOUT
 Processor Memory

Bus

I/O device 1 I/O device n

Figure. A single­bus structure
Hardware required to connect an
I/O device to the bus

Figure
• Address decoder
• Control circuits Interface
• Data and status registers circuit
 Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

Figure.  I/O interface for an input device.
Illustration of program-controlled
I/O

• I/O operations involving a keyboard and a

display device in a computer system.
 DATAIN

DATAOUT

STATUS DIRQ KIRQ SOUT SIN

CONTROL DEN KEN

7 6 5 4 3 2 1 0

Figure. Registers in keyboard and display interfaces         
 Move #LINE, R0 Initialize memory pointer.

W AITK TestBit #0,STATUS Test SIN.

Branch=0 W AITK Wait for character to be entered.
Mo ve DA TAIN,R1 Read c
haracter.
WAITD TestBit #1,STATUS Test SOUT.
Branch=0 WAITD Wait for display to becomeready.
Move R1,D ATAOUT Send character to display.
Move R1,(R0)+ Store character and advance pointer.
Compare #$0D,R1 Check if Carriage Return.
Branch≠ 0 W AITK If not, getanother character.
Move #$0A,D A T A OUT Otherwise, send Line Feed.
Call PROCESS Call asubroutine to process
theinput line.

re. A program that reads one line from the keyboard stores it in memory buffer
and echoes it back to the display.
 Program-controlled I/O
• Processor repeatedly checks a status flag to
achieve synchronization between the
processor and I/O device
• Processor polls the device
 INTERRUPTS
• Hardware signal
• Sent by I/O device to alert the processor
when it becomes ready
• Processor can utilize waiting period to
perform other useful functions
 Interrupts (cont.)
• Interrupt Service Routine
• Interrupt-request line
• Interrupt-acknowledge signal
• Interrupt vs. subroutine
• Interrupt latency
• Interrupt vs. Exception
 Example to illustrate interrupts
Program 1 Program 2

COMPUTE routine PRINT routine
(ISR)
1
2

Interrupt
occurs i
here
i +1

Figure. Transfer of control through the use of interrupts.
 Types of Exceptions
• I / O device request
• Invoking an operating system service from
a user program
• Tracing instruction execution
• Breakpoint(programmer-requested)
• Integer arithmetic overflow / underflow
• Power failure
 Interrupt Hardware
V
dd

Processor

INTR
INTR

INTR1 INTR2 INTR n

Figure. An equivalent circuit for an open­drain bus used
to implement a common interrupt­request line.
 Open-drain bus to implement
interrupt-request line
• INTR1 to INTRn – Interrupt request signals
• INTR = INTR1 + … + INTRn
• Open collector(bipolar circuits) or open-
drain(MOS circuits)
• Pull-up resistor R
 Enabling and Disabling
Interrupts
• Is it necessary?
• How?
• Interrupt-enable and Interrupt-disable
functions
 Enabling and Disabling Interrupts(cont.)

• Option 1
– Have processor ignore interrupt-request line
until execution of first instruction of ISR
– Use interrupt-disable instruction as first
instruction in ISR
– Use interrupt-enable instruction as last
instruction in ISR before Return-from-interrupt
 Enabling and Disabling Interrupts(cont.)

• Option 2
– Have the processor automatically disable
interrupts before starting execution of ISR
– PS register
• Option 3
– Processor has an edge-triggered interrupt-
request line
 Handling multiple devices
• How can the processor recognize the device requesting an
interrupt?

• How can the processor obtain the starting address of the

appropriate routine for each device?

• Should a device be allowed to interrupt the processor while

another interrupt is serviced?

• How should two or more simultaneous interrupt requests

be handled?
Handling multiple devices(cont.)
• Polling

• Vectored interrupts
– Code supplied by the device over the bus
– Interrupt Vector code
Handling multiple devices(cont.)
• Interrupt Nesting
– Device that sends interrupt requests to the
processor at regular intervals
– Priority structure for I/O devices
– Processor – user & supervisor modes
– Privileged instructions
 INTR1 INTRp
Processor

Device 1 Device 2 Devicep

INTA1 INTAp

Priority arbitration
circuit

Figure .
  Implementation of interrupt priority using individual
interrupt­request and acknowledge lines.
Handling multiple devices(cont.)

• Simultaneous Requests
– How does the processor decide which request
to service first?
– Daisy chain
 INTR
Processor

Device 1 Device 2 Devicen

INTA

(a) Daisy chain

Figure. Interrupt priority schemes.
 INTR 1

Device Device
INTA1
Processor

INTRp

Device Device
INTAp
Priority arbitration
circuit

(b) Arrangement of priority groups

Figure. Interrupt priority schemes.
 Controlling device requests
• Idle devices must not be allowed to
generate interrupt requests
– Device end
– Processor end
 Main Program

Move #LINE,PNTR Initialize bufferPointer.

Clear EOL Clearend-of-line indicator.
BitSet #2,CONTROL Enable keyboard interrupts.
BitSet #9,PS Set in
terrupt-enable bit in the PS.
..
.
Interrupt-serviceroutine

READ MoveMultiple R0-R1, – (SP) Saveregisters R0 and R1 on Stack.

Move PNTR,R0 Load address pointer.
MoveByte DATAIN,R1 Get input character and
MoveByte R1,(R0)+ store it inmemory.
Move R0,PNTR Update pointer.
CompareByte #$0D,R1 Check ifCarriageReturn.
Branch≠ 0 RTRN
Move #1,EOL Indicate end of line.
BitClear #2,CONTR OL Disable keyboard interrupts.
RTRN MoveMultiple (SP)+,R0-R1 Restoreregisters R0 and R1.
Return-from-interrupt

gure. Using interrupts to read a line of characters from a keyboard

 Exceptions
• How is it different from interrupt?
– Recovery from Errors
– Debugging
• Trace
• Breakpoints
– Privilege exceptions
• Supervisor mode of processor
 D.M.A.
• Direct memory access
• No intervention by processor
• DMA controller
• Cycle stealing
• Block or burst mode
 31 30 1 0

Status and control

IRQ Done
IE R/ W

Starting address

Word count

Figure. Registers in a DMA interface.
 Main
Processor
memory

System bus

Disk/DMA DMA
controller controller Printer Keyboard

Disk Disk Network

Interface

Figure. Use of DMA controllers in a computer system.

 Bus arbitration
• Bus master
• Bus arbiter

 Centralized arbitration
 Distributed arbitration
 BBSY

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2

Figure. A simple arrangement for bus arbitration using a daisy chain.
 Time

BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Figure. Sequence of signals during transfer of b
us mastership
for the de
vices in previous Figure.
V
cc

ARB 3
ARB 2
ARB 1
ARB 0
Start­Arbitration

O.C.

0 1 0 1 0 1 1 1

Interface circuit
for device A

     Figure.  A distributed arbitration scheme.
 BUSES
• Data lines
• Address lines
• Control lines
–R/W
– Operand size
– Timing information
• Master(initiator) and slave(target)
 Synchronous Bus
• All devices derive timing information from
a common clock line.
 Time

Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle

Figure 4.23. Timing of an input transfer on a synchronous bus.
 Time

Bus clock

Seen by master t
AM
Address and
command

Data
t
DM

Seen by slave
t
AS
Address and
command

Data
t
DS

t t t
0 1 2

Figure. A detailed timing diagram for the input transfer of Figure 4.23.
Multiple-Cycle Transfers Time

1 2 3 4

Clock

Address

Command

Data

Slave­ready

Figure. An input transfer using multiple clock cycles.
 Asynchronous Bus

• Handshake between master and slave

• Two timing control lines:
– Master-ready
– Slave-ready
 Time

Address
and command

Master­ready

Slave­ready

Data

t t t t t t
0 1 2 3 4 5

Bus cycle

Figure. Handshake control of data transfer during an input operation.
 Time

Address
and command

Data

Master­ready

Slave­ready

t0 t1 t2 t3 t4 t5

Bus cycle

Figure. Handshake control of data transfer during an output operation.
 INTERFACE CIRCUITS
• Circuitry required to connect an I/O device
to a computer bus
• Ports
– Serial port
– Parallel port
 Parallel Port

 Next page …
 Data

Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master­ready circuit
Valid
Input
Slave­ready
interface

Figure. Keyboard to processor connection.
 D AT AIN

D7 Q D
7 7

K e yboard
data

D0 Q0 D0

SIN
Status V alid
flag
Sla ve­
ready 1

Read­
status
Read­
data

R/W
Master ­
ready

A31

Address
decoder

A1

Figure 4.29. Input interface circuit
A0
 Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master
­ready
Output Idle
Sla v e­ready interf ace

Figure . Printer to processor connection.
Figure. Output interface circuit
 Bus
D7 P A7

D A TAIN
D1
D0 P A0

SIN
Input
status CA

PB7

D A TA OUT

PB0
SOUT

Handshak e CB1
control CB2
Sla ve­
Ready 1

Master ­
Ready
R/W

A31
My­address
Address
decoder Figure.  Combined input/output 
              interface circuit.
A2

RS1
A1

RS0
A0
 D7 P7

DATAIN

D0 P0

D ATAOUT

Data
Direction
Register

My­address
Figure. A general 8­bit parallel interface
RS2
RS1 Status C1
Register
RS0 and
select control
R /W C2
Ready
Accept

INTR
 DATAOUT

D7 D7 Q7

Printer
data

D0 D1 Q1
D0 D0 Q0

SOUT
Handshake Idle
control Valid
Read Load
status data

R/W

Slave­
ready
Go
A31
Address My­address Timing
decoder Logic My­address
A1

A0 Idle Respond
Go=1
Clock

Figure 35. A parallel point interface for the bus of Figure 25,
  with a state­diagram for the timing logic.
 Time

1 2 3

Clock

Address

R/W

Data

Go

Slave­ready

Figure 36. Timing for the output interface in Figure 35.
 Serial Port

 Next page…
 Serial
Input shift register input

DATAIN

D7
Figure. A serial 
D0
            interface.

DATAOUT
My­address
RS1
RS0 Chip and
register Serial
R /W Output shift register output
select
Ready
Accept

Status Receiving clock
I NTR and
control
Transmission clock
 Standard I/O interfaces
• Bridge
• ISA(Industry Standard Architecture) – PC AT
• IEEE
• ANSI
• ISO
 Widely used bus standards

• PCI

• SCSI

• USB
 Main
Processor
memory

Processor  bus

Bridge

PCI  bus

Additional SCSI Ethernet USB ISA

memory controller interface controller interface

SCSI bus
IDE
disk
Video
Disk CD­ROM
controller controller

CD­
Disk 1 Disk 2 ROM Keyboard Game

Figure .  An example of a computer system using different interface standards.
 PCI Bus
• Peripheral Component Interconnect
• Introduced in 1992
• Low-cost bus
• Processor independent
• Plug-and-play capability
 Host

Main
PCI bridge
memory

PCI bus

Ethernet
Disk Printer
interface

Figure 39. Use of a PCI bus in a computer system.
 Table 4.3. Data transfer signals on the PCI bus.

Name F
unction

CLK A 33-MHz or 66-MHz clock.

FRAME# Sent by the initiator to indicate the duration of a

transaction.

AD 32address/data lines, which may beoptionally

increased to 64.

C/BE# command/byte-enable
4 lines (8 for a 64-bit bus).

IRD Y#, TRD Y# Initiator-ready and Target-readysignals.

DEVSEL# A response from the device indicating that it has

recognized its address and is ready for a data
transfertransaction.

IDSEL# Initialization Device Select.

 1 2 3 4 5 6 7

CLK

Frame#

Adress #1 #2 #3 #4
AD

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

Figure 40. A read operation on the PCI bus.
 1 2 3 4 5 6 7 8 9

CLK

Frame#

Adress #1 #2 #3 #4
AD

C/BE# Cmnd Byte enable

IRDY#

TRDY#

DEVSEL#

Figure 41. A read operation showing the role of IRDY# / TRDY#
 PCI Bus …

• Data Transfer
• Device Configuration
• Electrical Characteristics
 SCSI Bus
• Small Computer System Interface
• Defined by ANSI – X3.131
• 50, 68 or 80 pins
• Max. transfer rate – 160 MB/s, 320 MB/s.
 Table 4. The SCSI bus signals.

Category Name u
Fnction

Data – DB(0)to Datalines:Carryonebyteofinformation

– DB(7) duringtheinformationtransfer
phaseand
identifydeviceduring
arbitration,
selection
and
reselectionphases
– DB(P) Parity bitforthedatabus
Phase – BSY Busy:Asserted
whenthebusisnotfree

– SEL Selection:
Asserted
duringselection
and
reselection

Information – C/D Con

trol/Data:Assertedduring
transferof
type controlinformation
(command,statusor
message)

– MSG Message:indicates
thatthe
information being
transferred
isamessage
 Table 4. The SCSI bus signals.(cont.)

Category Name u
Fnction

Handshake – REQ Request:Assertedby atargettorequestadata

transfercycle

– ACK Ackno
wledge:Assertedbytheinitiatorwhenit
hascompletedadatatransferop
eration

Direction of – I/O Input/Output:

Assertedtoindicateaninput
transfer op e to theinitiator)
eration(relativ

Other – ATN Attention:Assertedby aninitiatorwhenit

wishestosendamessageto atarget

– RST Reset:Causesalldevicecontrols todisconnect

fromthebusandassumetheirstart-up
state
 SCSI Bus(cont.)
• Bus signals
• Arbitration
• Selection
• Information Transfer
• Reselection
 Targets examine ID

DB 2

DB 5

DB 6

BS Y

S EL

Free Arbitration Selection

Figure 42. Arbitration and selection on the SCSI bus.
   Device 6 wins arbitration and selects device 2.
 USB
• Universal Serial Bus
• Speed
• Low-speed(1.5 Mb/s)
• Full-speed(12 Mb/s)
• High-speed(480 Mb/s)
• Port Limitation
• Device Characteristics
• Plug-and-play
 Host computer

Root
hub

Hub Hub

I/O I/O I/O I/O

Hub device device device device

I/O I/O
device device

Figure 43.  Universal Serial Bus tree structure.
 Host computer

Root
Hub

HS HS

Hub A Hub B

HS F/LS

HS ­ High speed
F/LS ­ Full/Low speed

De vice De vice
C D

Figure 44.  Split bus operation
 USB(cont.)

• Addressing

• USB Protocols
 PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3

(a) Packet identifier field 

Bits 8 7 4 5

PID ADDR ENDP CRC16

(b)  Token packet, IN or OUT

Bits 8 0 to 8192 16

PID DATA CRC16

(c) Data packet

Figure 45.  USB packet format.
 Host Hub I/O Device

Token
Data0

ACK
Time
Token
Data0

ACK

Token
Data1
Figure . An 
             output 
ACK               transfer
Token
Data1

ACK
 USB(cont.)

• Isochronous Traffic on USB

– USB frame
• Electrical Characteristics
 Bits 8 11 5

PID Frame number CRC5

(a) SOF Packet

1­ms frame

S T3 D T7 D S T3 D

S ­ Start­of­frame packet
Tn­ Token packet, address = n
 
D ­ Data packet
A ­  ACK packet

(b) Frame example

Figure 47.  USB frames.
 The only person who
never makes a mistake
is the person who never does
anything…!
- Theodore Roosevelt