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 Since the invention of Von Neumann architecture, it is being

used for general purpose microprocessors for nearly three
decades. It is the first and most popular architectures.

- It simplifies the Microcontroller chip design because only

one memory is accessed.

- Data and instructions are fetched from one memory only.

- The contents of RAM can be used for both variable storage as

well as program instruction storage.

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 Von Neumann machines store program and data in the same
memory area with a single bus

 An instruction contains the operation command and the

address of data to be operated on (operand)

 Most of the general-purpose microprocessors such as Motorola

68000 and Intel 80x86 use this architecture

 It is simple in hardware implementation, but the data and

program are required to share a single bus

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 Address bus

200 Program
ADD r5,r1,r3 Data bus 200 Counter
CPU
IR
Memory ADD r5,r1,r3

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 The basic Von Neumann architecture has one serious
disadvantage: everything happens consecutively.
 Only one process (fetch, decode or execution) takes place at a
clock cycle.
 Limited data paths. These will limit the processing power of the
processor. The performance of a micro-processor depends on
word length (number of bits in a data) clock speed (frequency),
internal bus architecture and the interfaces to peripherals.
Execution time is used to assess the performance of a
microprocessor.

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 Harvard allows two simultaneous memory fetches:
Code and data bus are separate

 Greater amount of instruction parallelism is possible is

in this architecture.

 Most DSPs use Harvard architecture for streaming

data:
 greater memory bandwidth
 Data and program do not compete for the same port
(used in  speech processing  DSP)

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 The only difference in Harvard architecture is that program
and data memories are separated and use physically separate
transmission paths

 Enables the machine to transfer instructions and data

simultaneously-- enhances performance

 The Harvard architecture is more commonly used in

specialized microprocessors for real-time and embedded
applications

 However, only the early DSP chips use the Harvard

architecture because of the cost

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 Cost penalty with the Harvard architecture, which needs twice
as many address and data pins on the chip

 To balance cost and performance, modified Harvard

architecture is used in most DSPs

 Uses single data and address bus externally but internally there
are two separate busses for program and data

 The separation of program and data information is done by

timing (multiplexing)

 For one clock cycle, program information flows on the pins,

and in second cycle data follows on the same pins

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 address
data memory
data PC

CPU Points to
address Program
memory-
program memory not data
data memory

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 Von Neumann & Harvard Architectures

ALU I/O ALU I/O

Address bus Data bus

instructions
instructions data
and
data

Von Neumann architecture Harvard architecture was coined to

Area efficient but requires higher bus describe machines with separate
bandwidth because instructions and memories.
data must compete for memory. Speed efficient: Increased
parallelism.
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Instruction Architecture

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 Reduced Instruction Set Computer

 By reducing the number of instructions that a processor

supports and thereby reducing the complexity of the chip,

 it is possible to make individual instructions execute

faster and achieve a net gain in performance

 even though more instructions might be required to

accomplish a task.

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 RISC Features
• Large register set: having more registers allows memory
access to be minimized.
• Load/Store architecture: operating data in memory
directly is one of the most expensive in terms of clock
cycle.
• Fixed length instruction encoding: This simplifies
instruction fetching and decoding logic and allows easy
implementation of pipelining.
All instructions are register-to-register format
except Load/Store which access memory
All instructions execute in a single cycle
except branch instructions which require two.
Almost all single instruction size.
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 Complex Instruction Set Computer

Philosophy: Hardware is always faster than the software.

Instruction set should be as powerful as possible
With a power instruction set, fewer instructions are needed to
complete (and less memory) the same task as RISC.
• CISC was developed at a time (early 60’s), when memory
technology was not so advanced.
• Memory was small (in terms of kilobytes) and expensive.
But for embedded systems, especially Internet Appliances,
memory efficiency comes into play again, especially in chip area
and power.
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 Comparison
CISC RISC

Any instruction may reference memory Only load/store references memory

Many instructions & addressing modes Few instructions & addressing modes

Variable instruction formats Fixed instruction formats

Single register set Multiple register sets

Multi-clock cycle instructions Single-clock cycle instructions

Micro-program interprets instructions Hardware executes instructions

Complexity is in the micro-program Complexity is in the CPU

Less to no pipelining Highly pipelined

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Which is better
RISC

Or
CISC
?

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 Analogy

Construct a 5 foot wall

Method A: a large amount of small concrete blocks.
Method B: a few large concrete blocks.
Which method is better?

The amount of work done in either method is equal

Method A: more blocks to stack but easier and faster
to carry.
Method B: fewer blocks to stack but the process is
slowed by the weight of each block.
The distinction is in the dispersal of the work done.
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 RISC versus CISC

RISC machines: SUN SPARC, SGI Mips, HP PA-RISC, Microchip

PIC 16C7X, 16F8XX, Siemens C166.
CISC machines: Intel 80x86, Motorola 680x0
CISC occurs whenever there is a disparity in speed
 between CPU operations and memory accesses
 due to technology or cost.
What about combining both ideas?
CYRIX and Intel’s latest microcontrollers have an architecture which
is externally CISC but internally RISC & CISC!

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 How to boost performance beyond the fastest clock speeds
afforded by the processor ?

 By increasing the processors’ parallelism in one of the following

ways:
- Increase the number of operations that can be performed
in each instruction.
- Increase the number of instructions that can be issued
and executed in every machine cycle.

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Instruction Pipelining is to allow more than one instruction to be
in some stage of execution at the same time in the CPU.

 Laundry Example A B C D
 Ann, Brian, Cathy, Dave
each have one load of clothes
to wash, dry, and fold
 Washer takes 30 minutes

 Dryer takes 30 minutes

 “Folder” takes 30 minutes

 “Stasher” takes 30 minutes
to put clothes into drawers

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 6 PM 7 8 9 10 11 12 1 2 AM

30 30 30 30 30 30 30 Time
T
a A
s
k B
C
O
D
r
d
e
r
 Pipelined laundry takes 3.5 hours for 4 loads!
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 Pipelining doesn’t help latency of single task, it helps
throughput of entire workload
 Multiple tasks operating simultaneously using different
resources
 Potential speedup = Number pipe stages
 Pipeline rate limited by slowest pipeline stage
 Unbalanced lengths of pipe stages reduces speedup
 Time to “fill” pipeline and time to “drain” reduces speedup

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