7.chapter7 - Operational Amplifier

ĐẠI HỌC QUỐC GIA TP.
HỒ CHÍ MINH
ĐẠI HỌC BÁCH KHOA
NGÀNH KỸ THUẬT ĐIỆN TỬ
CHƯƠNG 7
BỘ KHUẾCH ĐẠI
THUẬT TOÁN (OPAMP)
Hoàng Trang
Bộ môn Kỹ Thuật Điện Tử
hoangtrang@hcmut.edu.vn
1
TP.Hồ Chí Minh 03/ 2014
Overview
Review
This chapter discusses about the response of single stage and
differential amplifiers in the frequency domain.
Following a brief review of basic concepts, we describe in this

chapter some kind of single-stage circuit include:
• Common-Source.
• Common-Gates.
• Common-Drain.
Then, analyze the high-frequency behavior of
•Cascode amplifier.
•Current Mirror
•Differential amplifier.
Faculty of Electronics Engineering Spring 2014 Analog Integrated Circuit Design Course
2
Outline
1. Introduction.
2. Common Source Stage.
3. Common Gate Stage.
4. Common Drain Stage.
5. Cascode Amplifier.
6. Current Mirror
7. Differential Amplifier.
3
1. Introduction
Basic Theorem
(1) Voltage amp : Vo = Avd * (Vi+ - Vi-)
(2) Differential input, single-ended output
(3) Fully differential OP amp: diff output
Ideal OP amp :
(1) Differential mode voltage gain: infinity
(2) Common mode voltage gain: 0
(3) Input resistance: infinity
(4) Output resistance: 0
(5) Bandwidth: inifinity
4
1. Introduction
Basic Theorem
General purpose OP amp :

(1) example 741 OP amp
(2) small Rout to drive any load including R load
(3) needs output stage
CMOS OP amp :
(1) usually drive on-chip capacitive load only
(2) large Rout -> current output -> OTA
(operational transconductance amplifier)
(3) does not need output stage
5
2. Compensation Opamp
Gain Error
A1=infinity -> gain=1+(R1/R2)
A1=? for gain error < 1%
6
Gain Error
A1=? for gain error < 1%
for gain error < 1%
7
Bandwidth
Single pole characteristic assumed
8
Bandwidth
Step response
9
Bandwidth
Step response
reduced by 1+(loop gain)
10
Design Note
Simple differential pair : voltage gain not enough (< 20 for

submicron devices)
For high gain
1-stage cascode OP amp (gain boost optional) (telescopic

OP amp, folded cascode OP amp)
reduced output swing
11
3. Opamp Architecture
Two-Stages Opamp
2-stage OP amp : pro -> high gain + large output swing
2-stage OP amp :
Requires frequency compensation (Miller pole-splitting

frequency compensation
12
CMOS Level 2-stages Opamp
13
Fully Differential 2-Stages Opamp
14
Single End 2-Stages Opamp
15
Cascode (Telescopic) OP amp
16
2-stage OP amp (cascode 1st stage)
17
2-stage OP amp (fully differential)
18
NMOS-input Folded cascode OP amp
(1) Input common mode range: extended up to VDD

(2) Output voltage range increased compared to telescopic
19
PMOS-input Folded cascode OP amp
(1) Input common mode range: extended down to VSS

(2) Output voltage range increasedcompared to telescopic
20
4. Unity Gain - Buffer
The Unity Gain
Must meet both output swing requirement and input CM voltage

range requirement simultaneously
Telescopic OP amp : narrow output swing and narrow input common

mode range -> not suitable for unity gain buffer application (folded
cascode OK)
21
Using Simple Differential Pair
22
Using Simple Differential Pair
Assume the same VDSAT

(For open loop)
Input CM min: 2 VDSAT + VTH

Input CM max: VDD –VDSAT
Output min: 2 VDSAT

Output max: VDD –VDSAT
(For unity-gain feedback)
Vout min: 2 VDSAT + VTH (limited by input CM)

Vout max: VDD –VDSAT
Vout swing: VDD –3 VDSAT - VTH
Unity gain buffer using
23
Using Telescopic Opamp
24
Using Telescopic Opamp
Assume the same VDSAT
(For open loop, optimum Vb)
Input CM min: 2 VDSAT + VTH

Input CM max: VDD –3 VDSAT – VTH
Output min: 3 VDSAT

Output max: VDD –2 VDSAT - VTH
(For unity-gain feedback , optimum Vb)
Vout min: 2 VDSAT + VTH (limited by input CM)

Vout max: VDD –3 VDSAT –VTH (limited by input CM)
Vout swing: VDD –5 VDSAT –2 VTH (severely limited)
Unity gain buffer using telescopic OP am
25
5. Design Example
5.1 Specification
1. Gain at dc, Av(0)

2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, CL
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, Pdiss
Đặc tả kỹ thuật Giá trị
DC Gain 70 dB
Vdd 1.8
PM (Phase Margin) 60 deg
GB (Gain Bandwidth) 5 MHz
CL (Load Capacitance) 10 pF
SR (Slew Rate) 10 V/us
Voltage Swing 0.5 – 1.3 (V)
ICMR 0.8 – 1.5 (V)
26
5. Design Example
5.2 Analysis the Architecture
The Schematic
27
5. Design Example
5.2 Analysis the Architecture
Define the Relationship of the Design
28
5. Design Example
5.3 Hand Calculation
29
5. Design Example
5.3 Hand Calculation
30
5. Design Example
5.3 Meet Specification?
31
5. Design Example
5.4 CMOS Level Design
32
5. Design Example
5.4 Silmulation
33
5. Design Example
5.5 Layout
34
5. Design Example
5.5 Layout
35
References
[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

2nd Edition, Oxford Univeristy Press, 2002.
[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

International Edition, Electrical and Computer Engineering Series,
McGraw-Hill, 2001
[3] R. Jacob Baker. "CMOS Circuit Design, Layout, and Simulation", 3rd
Edition, IEEE Press Series on Microelectronic Systems, A Join Wiley &
Son, 2010 .

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ĐẠI HỌC QUỐC GIA TP.

Following a brief review of basic concepts, we describe in this

General purpose OP amp :

A1=infinity -> gain=1+(R1/R2)

A1=? for gain error < 1%

A1=? for gain error < 1%

for gain error < 1%

Single pole characteristic assumed

reduced by 1+(loop gain)

Simple differential pair : voltage gain not enough (< 20 for

For high gain

1-stage cascode OP amp (gain boost optional) (telescopic

reduced output swing

Requires frequency compensation (Miller pole-splitting

(1) Input common mode range: extended up to VDD

(1) Input common mode range: extended down to VSS

Must meet both output swing requirement and input CM voltage

Telescopic OP amp : narrow output swing and narrow input common

Assume the same VDSAT

Input CM min: 2 VDSAT + VTH

Output min: 2 VDSAT

(For unity-gain feedback)

Vout min: 2 VDSAT + VTH (limited by input CM)

(For open loop, optimum Vb)

Input CM min: 2 VDSAT + VTH

Output min: 3 VDSAT

(For unity-gain feedback , optimum Vb)

Vout min: 2 VDSAT + VTH (limited by input CM)

1. Gain at dc, Av(0)

Define the Relationship of the Design

[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

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