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MOSFET DEVICE

CHARACTERISTI
CS AND MOS
INVERTERS
TOPICS TO BE COVERED
SYMBOLS OF BJT AND MOS.
DERIVING MOS Id-Vds CHARACTERISTICS.(IN GRAPH VIEW).
TRANSLINEARITY PRINCIPLE.
MOS CAPACITOR
MOSFET.
DERIVING MOS Id-Vds CHARACTERSTICS(IN DEVICE POINT OF VIEW).
Short channel effects.
Velocity saturated MOSFET.
MOSFET in subthreshold region.
Introduction to FINFET.
INVERTER.
WHY GAIN  IS NECESSARY FOR NOISE MARGIN.
Noise Margin derivations 
Let us represent an amplifier in its y parameter model.
 DERIVATION OF In order to have V2/V1 maximum the following conditions are to
MOS   Id-Vds be satisfied.
CHARACTERISTIC 1.y11=0.( dIg/dVgs=0)
S.(IN GRAPH 2.y12=0.(unilateral device no feedback).
VIEW). 3.y21=infinite.(dId/dVds)(transconductance is infinite.)
4.y22=0.(o/p resistance is infinite).
Continued....
Now let us draw a graph between output current and output voltage using those four
constraints.

                                                                                      
                                                                                      
                                                           
Continued.
Since y22 is zero, the slope of the line should be zero. But  if it continues for
negative vds also then the graph enters the 2nd quadrant. But due to passivity of
the MOS  the graph should lie in 1st and 3rd quadrants only. So, the line is
parallel to the x axis for some portion and then comes down to zero trying to
come into 3rd quadrant.
Condition for Passivity:
v1.i1+v2.i2>0.
But for MOSFET as i1 which is gate current it is zero so v2.i2>0
That means the vds.id>0. So, the graph between vds and id should not lie in 2nd
quadrant.
Deriving MOS characteristics(Device
point of view)
We know that y22=0 and y21=infinite.
That means that the output current should be more sensitive to input voltage in
other words it should be controlled by  input voltage  and it should be very less
sensitive to output voltage.
So, we should somehow achieve this.
Field effect is technique invented by Julius Edgar Lilienfeld which is given in
one of his patent.
Let us discuss what is field effect.
Continued...
Let us take a N type
semiconductor.
Let us apply a
voltage across it. It
simply acts as resistor.
Continued..
Now let us bring some
 other conductor
nearer to this
semiconductor but not
touching. Let us for
time being do not
worry about how to
hold it without
touching and keeping it
nearer. Now let us
apply a voltage across
it let us investigate
what happens now.
Continued..
The electrons will be
repelled from the
surface and at the
surface the positively
charged ions will be
present. Those
electrons will appear
on the metal plate as
there is a close path.
Continued....
Now as we go on
increasing the voltage
across gate further
more ions will be
depleted of carriers
and depletion region
increases.
Continued..
By applying a negative voltage, the conductivity decreased as the free electrons
concentration decreased
If we apply a positive voltage, we can increase the conductivity
So by changing the voltage across the third terminal, we can change the
conductivity between two terminal which is an important characteristic of
"TRANSISTOR".
By applying an electric field ,the conductivity, the resistance, current flow can be
modulated. This principle is called "FIELD EFFECT PRINCIPLE".
Link to FET patent
https://www.computerhistory.org/siliconengine/field-effect-semiconductor-device-concepts-pat
ented/
Continued..
Will this happen forever????Will the depletion region goes on increasing????
Wait we have another source of positive charge besides positively charged ions..
HOLES!!!!!!.But from where they can come from as it is an n type substrate..
They can come from thermal generation.
So, as vg increases further holes generated thermally will come to the surface and depletion
region starts shrinking as this is energetically preferred state.. 
Continued...
Now we can control the concentration of holes so the current through gate
voltage.
Our aim is achieved.
Till now we discussed about MOS capacitor.
But this is a very slow process. Holes should be generated thermally and should
all away come to the surface.
So, the idea is to have two heavily doped p type diffusions under the metal
contacts so that they can supply the holes and it is fast. This is the idea of
MOSFET.....
So, finally we have designed the MOSFET!!!!!
In next slide let us see NMOSFET.
NMOSFET
Stage1-Formation of Depletion layer
Stage-2:enhancing depletion region
Stage3-Formation of inversion layer
                            np=ni^2.
                     INVERTER(Noise Margin)
  
Noise Margin is the amount of noise that a CMOS
circuit could withstand without compromising the
operation of the circuit

Presence of noise margin does make sure that any


signal which is logic '1' with finite noise added to
it, is still recognized as logic '1' and not as logic '0'
We can see that if noise is added to this, the noise propagates
throughout. Noise rejection is not present. So, it is a bad
inverter.
Continued..
This is a practical inverter where gain is not strictly zero, but less than
one in some portions. This doesn't provide  better noise immunity when
compared to the previous one but is definitely a lot better than the linear
one.
Inverter Threshold Voltage 
Continued..
Continued..
Inverter Threshold Voltage for a Practical
CMOS
Noise Margin of Ideal CMOS
Noise Margin of Practical CMOS
Continued..
Noise Margin Derivation
Method for finding threshold values

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