Writing Engineering Abstracts(15)

http://www.chineseowl.idv.tw

:
(+)





(+) WSNs have been extensively studied
owing to the potential applications such as in military surveillance,
elderly health care and house security. WSN devices largely operate
under resource-limited conditions. Computing capability, energy, and
communication bandwidth are the most precious resources. However,
a secure and energy-aware communication protocol on WSN is still
unavailable for practical applications. Therefore, this work
describes a novel security protocol, capable of cooperating efficiently
with other energy-conserving communication protocols. A complex
WSN is constructed to function as the operating platform. The
performance of three communication protocols is then evaluated when
operating with several security protocols, including the proposed one.
Next, the drained energy and timing cost are compared statistically to
yield the simulation results. Analysis results
indicate that the power consumption does not increase, and the
overhead on connection delay is under 20%.
Importantly, the proposed protocol can be adopted to establish the
foundation of energy-efficient and dependable WSNs.
(1 of 2)
(+) Time-to-market delivery in
semiconductor manufacturing is of priority concern in advanced
R&D technology development. Ensuring that products reach
time-to-market delivery goals requires that operational managers
and fabrication (fab) personnel fully support R&D experimental
lots (R&D Lot). Nevertheless, capacity shortage in a wafer fab
fails to comply with output requirements of customers, leading to
delays in the R&D lot schedule and the overall project. Although
an output-driven fab normally adopts Move and Turn Rates as
key performance indicators (KPI), such indicators fail to assess
the actual performance of R&D lots in monitoring R&D
experiments and ensuring prompt experimental delivery.
Therefore, in addition to constructing an effective performance
index, this work presents an optimal R&D Lot cycle time
reduction model capable of executing timely, effective and
clearly defined measures to achieve project cycle time,
regardless of whether in R&D or in a wafer fab.
(2 of 2)
X-factors are modified to determine the R&D cycle time and derive
the F-factor. Based on the two factors, a model is then constructed to
shorten technology development time and improve quality control
continuously by using the SPC chart as a monitoring mechanism. Next,
the on-time delivery performance of a wafer fab for an advanced R&D
technology is determined using the X-factor (XFab), excluding R&D
handling time (HT_RD). Additionally, the F-factor is used to monitor the
maturation process of advanced R&D technology manufacturing and
reduce lot inventory costs. Simulation results
indicate that the proposed performance indices can accurately forecast
the R&D lot schedule, shorten lot cycle time and ensure time-to-market
delivery of advanced technology products. KPI design provides global
optimization benefits that link R&D and the wafer fab.
Importantly, the proposed performance index can ultimately
shorten R&D cycle time and enhance the on-time delivery of advanced
technology products by fab-run R&D Lots. Given R&D technology
trends to enhance product quality and manufacturing maturity through
KPI design, enterprises can exploit these factors to upgrade operational
performance in semiconductor manufacturing.
Further details can be found at
http://www.chineseowl.idv.tw