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Difference Between 8085 and 8086
‡ The most significant difference between the Intel 8085 and 8086
microprocessors is that the 8085 is an 8-bit system, NMOS
microprocessor and the 8086 is a 16-bit system, HMOS
microprocessor. This difference allows the 8086 system to have a
much larger set of operational instructions and can make
calculations to more significant places.

‡ 8085 contains 16-bit address bus and 8-bit data bus .8086 contains
20-bit address bus and 16-bit data bus.

‡ In 8085 the clock speed is 3MHZ where as in 8086 the clock speed
is 5MHZ.

‡ An 8085 processor has 6,500 transistors in its programming circuit


boards, compared with 29,000 transistors in an 8086 processor. This
means there are roughly 4.5 times more transistors in an 8086
processor, leading to a much faster processing rate.
‡ 8086 has a special concept called as memory segmentation. It
allows parallel processing, while 8085 does not.

‡ 8085 consists 74 instructions. 8086 consists 117 instructions. In 8086


four 16 bit registers are available and pin no 33- min/(~max) it selects
minimum mode when this pin is high otherwise it selects maximum mode.
‡ 8086 has 4 segment registers which are not peresent in 8085. also it has
preftech queue which stores instructions ahead of time which is not present
in 8085. The BIU and execution unit in 8086 works parallely which improves
its performance.

‡ Pipelining concept is not seen in 8085 and


‡ The 8086 had more registers and many more instructions.

‡ Both processors require a 5-volt power supply and both have a 40-pin
DIP, or dual inline package, which is how they plug into the circuit board in
the computer or device where they are being used. They also are both
roughly from the same era of computing and are now outdated.
Pin Diagram of 8086
JD15-JD0
ADDRESS DATA BUS: These lines constitute
the time multiplexed memory or i/o address
and data bus .
J  (ADDRESS LATCH ENABLE): A HIGH on
this line causes the lower orders 16-bit address
bus can be used as data bus.
RJDY : READY is the acknowledgement
from the addressed memory or i/o device that
will be complete the data transfer .
INTR : INTERRUPT REQUEST is a level
triggered input which is sample during the last
clock cycle of each instruction to determine if
the processor should enter into interrupt
acknowledgment operation .
INTJ : INTERRUPT ACKNOWLEDGEMENT
from the mp.
RST : It causes the processor to
immediately terminate its present activity.
Pin Diagram of 8086
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I. Signals common for both minimum & maximum mode.


1. AD15-AD0 :
    
  
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*          *       
2. A19/S6, A18/S4, A17/S4, A16/S3
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‡ These lines float at tristate off during the local bus hold acknowledge.

S4 S3 Indications
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% % ,

x. BHS7: Bus High nableStatus


The bus high enable signal is used to indicate the transfer of data over the higher order
(D15-D8) data bus.
Whole word = Upper Byte + Lower Byte

`  A0 Indication
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4. RD: Read
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5. RADY:


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6. RS:

+
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7. INR: Interrupt Request:

+
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8. S:

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9. NMI: Non-Maskable Interrupt
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10. CLK: Clock Input
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11. Vcc:
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12. GND:
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II. Minimum mode operation of 8086
1. M/IO-á

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2. INA: Interrupt Acknowledge



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3. AL: Address Latch nable



++
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4. D/R: Data transmit/Receive



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III.Maximum mode operation of 8086
1.S2, S1, S0: 

 
 
 
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2. LOCK: 
 


       

   

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  4"/A;  4"/A



   4"/A 


   

  
  

  

  
   
3   
7  *   8

3. QS1, QS0 : Queue status  





     
3:    
 
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 3
:

4. RQ/G0, RQ/G1: Request/Grant   


      
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Jrchitecture of 8086:
The 8086 is divided into two units ±ecution Unit (U) & Bus Interface Unit
(BIU). Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as Pipelining. This
results in efficient use of the system bus and system performance.

‡ The BIU fetches instructions, reads and writes data, and computes the
20-bit address.
‡ The U decodes and executes the instructions using the 16-bit ALU.

± Decodes instructions fetched by the BIU


± Generate control signals
± ecutes instructions

The BIU and execution unit in 8086 works parallely which improves its
performance.

The general purpoe register, Stack Pointer, Base Pointer, Index Register, ALU, Flag
Register, Instruction Decoder, an timing and control Unit constitute Execution unit.

The segment register, instruction pointer and 6byte instructionqueueare associated


with Base Interface Unit.
Jrchitecture :
Bus Interface Unit :
Π  
    
 
 
       

        

        

       

      
 


Segment Registers
8086 has segmented memory. 1MB memory is divided into
16 logical segments (16x64K)
ÀS ± Code Segment register used for addressing a memory
location in the code segment of the memory where the
executable program is stored.
SS ± Stack Segment register refers to stack segment of stack
data
DS ± Data Segment register point to the data segment of the
memory, where the data is resided.
S ± Extra Segment register also refers to a segment which
essentially is another data segment of the memory. (It also
points to data segment).
ecution Unit :
1. Àontrol circuit ± which directs internal operations.
2. Instruction Decoder ± translates instructions fetched from memory into a
series of actions which the EU carries out.
x. J U ± Add, sub, increment, decrement, complement, shift binary
numbers.
4. General Data Registers
AX = (AH+AL) Accumulator.
BX - used as an offset storage for forming physical address.
CX - default counter in case of string and loop instructions.
DX ± implicit operand or destination register in case of a few instruction.
5. Pointers and Inde Registers
Pointers contain offset within the particular segments.
IP ± Instruction Pointer register holds the 16-bit address or offset of the
net code byte within code segment .
20 bit address = offset of IP + Segment base address in CS.
BP ± Base Pointer contains Source Inde (SI) register and Destination
Inde (DI) register.
SP ± Stack Pointer register in the Execution Unit holds the 16-bit offset
from the start of the segment to the memory location where a word was
most recently stored on the stack (i.e top of stack).

SP,SI,DI ± these 3 register are used for temporary storage of data.


How to calculate Physical address
‡ Segment registers hold the base address of where a particular segment
begins in memory. There is the code segment (CS), data segment (DS),
stack segment (SS), and extra segment (ES).

Segment registers are 16-bit registers which are ASSUMED to be holding a


20 bit number, because it is assumed you will add a zero to the end. For
example, if CS register is holding the hexadecimal value "13A6", then this
value is actually representing the address "13A60".

To calculate a physical address, you take the address (called the logical
address) and add it to the segment address.
‡ For eample, if you wanted to calculate the physical address which relates
to logical address "1356" in the stack segment - you would also need to
know what value is in the SS register, lets assume "2345":

Add the zero to the end of the segment address:


23450
Then add the two addresses together:
23450 + 1356 = 247A6
‡ The physical address is calculated by finding out where the
segment starts, then adding to it the offset address.
‡ One of the segment registers will tell you where the segment
begins.
‡ Let's assume that the segment register is holding the value
"A45C". In this case, the segment begins at the 20 bit address
"A45C0".
‡ Add to that the offset address:
A45C0 + 4B32 = A90F2.
‡ Therefore the address A90F2 is the 20 bit physical address
that maps to the segment, offset address A45C:4B32
6. Flag Registers
A flag is a flip-flop that indicates some condition produced by the execution
of an instruction or controls certain operations of the EU.

A 16-bit flag register in the EU contains 9 active flags, 6 flags indicate


some condition produced by an instruction(conidtion flags), 3 flags are
control flags.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X Jc X P X Ày

O ± Overflow Flag
S ± Sign Flag
Z ± Zero Flag
Ac ± Auxiliary Carry Flag
P ± Parity Flag
Cy ± Carry Flag
D ± Direction
I ± Interrupt Flag
T ± Trap Flag
X ± Not used
Interrupts
The processor has the following interrupts :
‡ INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction. When an interrupt occurs, the processor stores
FLAGS register into stack, disables further interrupts, fetches from the bus one byte
representing interrupt type, and jumps to interrupt processing routine address of which
is stored in location 4 * <interrupt type>. Interrupt processing routine should return with
the IRET instruction.
‡ NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
‡ Software interrupts can be caused by:
‡ INT instruction - breakpoint interrupt. This is a type 3 interrupt.
‡ INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
‡ INTO instruction - interrupt on overflow
‡ Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt processing
routine.
‡ Processor exceptions: divide error (type 0), unused opcode (type 6) and escape
opcode (type 7).
‡ Software interrupt processing is the same as for the hardware interrupts.
Jddressing Modes of 8086 :
The way in which an operand is specified is called its addressing mode.
I. Data-related addressing modes
II. Branch addressing modes
I. Data-related addressing modes :
1. Immediate addressing mode
The datum is either 8 bits or 16 bits long and is part of the instruction.
2. Direct addressing modes
The 16 bit effective address (EA) of the datum is part of the instruction
x. Register addressing modes
The datum is in the register that is specified by the instruction.
4. Register Indirect
The effective address of the datum is in the base register BX or an index register that is
specified by the instruction.
5. Register Relative
The effective address is the sum of an 8 or 16 bit displacement and the contents of
base register or an index register.
6. Based Indeed
The effective address is the sum of a base register and an index register.
7. Relative Based Indeed
The effective address is the sum of an 8 or 16-bit displacement and a based indexed
address.
Instruction Set
Instruction set of Intel 8086 processor consists of the following
instructions:
1) Data moving instructions.
2) Arithmetic - add, subtract, increment, decrement, convert
byte/word and compare.
3) Logic - AND, OR, exclusive OR, shift/rotate and test.
4) String manipulation - load, store, move, compare and scan for
byte/word.
5) Control transfer - conditional, unconditional, call subroutine
and return from subroutine.
6) Input/Output instructions.
7) Other - setting/clearing flag bits, stack operations, software
interrupts, etc.
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