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8086 CPU has 8 general purpose registers

 - the accumulator register (divided into 

Arithmetic, logic and data transfer
Multiplication & Division
Input & Output

 - the base address register (divided into ).

BX register usually contains a data pointer used for based indexed or
register indirect addressing.

 - the count register (divided into ): Iterative code segments
using the LOOP instruction
Repetitive operations on strings with the REP command
Count (in CL) of bits to shift and rotate

 - the data register (divided into  ):

DX:AX concatenated into 32-bit register for some MUL and DIV
operations
Specifying ports in some IN and OUT operations


 


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- source index register: Can be used for pointer addressing of data
Used as source in some string processing instructions
Offset address relative to DS

- destination index register: Can be used for pointer addressing of data
Used as destination in some string processing instructions
Offset address relative to ES

 - base pointer: Primarily used to access parameters passed via the stack
Offset address relative to SS

 - stack pointer: Always points to top item on the stack

Offset address relative to SS
 |
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 - points at the segment containing the current program.

- generally points at segment where variables are defined.

- extra segment register, it's up to a coder to define its usage

.
- points at the segment containing the stack

 
  |
  

 - the instruction pointer: Always points to next instruction to be

FETCHED
Offset address relative to CS

 register always works together with  segment register

 Flag Register
Flag register contains information reflecting the current status of a
microprocessor. It also contains information which controls the
operation of the microprocessor.
15 0
Š Š Š OF DF IF TF SF ZF Š AF Š PF Š CF

A Control Flags A Status Flags

IF: Interrupt enable flag CF: Carry flag

DF: Direction flag PF: Parity flag
TF: Trap flag AF: Auxiliary carry flag
ZF: Zero flag
SF: Sign flag
OF: Overflow flag

Microprocessor System Design 3-5

 - this flag is set to  when there is an  !"#$!%#&. For example
when you add bytes '(() (result is not in range 0...255). When there is no overflow
this flag is set to *.

 + - this flag is set to  when there is even number of one bits in result,
and to * when there is odd number of one bits.

,   - set to  when there is an  !"#$!%#& for low nibble (4
bits).

-!#- - set to  when result is .!#. For non-zero result this flag is set to *.

  - set to  when result is !+ $!. When result is /# + $! it is set to *.
(This flag takes the value of the most significant bit.)
/ if set then single-step interrupt will occur after the next
instruction
The trap flag's state is used when using the x86's debugging features.

When set, the x86 processor will execute only one instruction at a time and
then call interrupt 1 (the debug interrupt) to allow an attached debugger to
inspect the program as it executes.

+!/+!0!
 - when this flag is set to  CPU reacts to interrupts
from external devices.i,e, setting this bit enables maskable interrupt.

!1+ #  - this flag is used by some instructions to process data

chains, when this flag is set to * - the processing is done forward, when this
flag is set to  the processing is done backward.
if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.

$!%#& - set to  when there is a  !"#$!%#&. For example,

when you add bytes **)(* (result is not in range -128...127).
 8086/8088 20-bit Addresses



m

   



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06/03/2005 ET4508_p2 (KR) 8

 Exercise: 20-bit Addressing

m
         
 

   ! 

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   #      
   ! 

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06/03/2005 ET4508_p2 (KR) 9

 General Purpose Registers
15 8 7 0
AX AH AL Accumulator

BX BH BL Base
Data Group
CX CH CL Counter

DX DH DL Data

SP Stack Pointer

BP Base Pointer
Pointer and
Index Group
SI Source Index

DI Destination Index

Microprocessor System Design 3-10

 Generating Memory Addresses
How can a 16-bit microprocessor generate 20-bit memory addresses?

!%+2 %+30 +
FFFFF

16-bit register 0000 Addr1 + 0FFFF

Segment
+ 16-bit register Offset Offset (64K)
Addr1

20-bit memory address Segment

address
00000

+!4*,456!6#""!!!+ # 6!6#/1!

Microprocessor System Design 3-11

 Memory Segmentation

Segment registers in BIU

15 0
CS Code Segment

DS Data Segment

SS Stack Segment

ES Extra Segment

Microprocessor System Design 3-12

 Memory Address Calculation

Segment addresses must be stored 0000

Segment
in segment registers address
Offset is derived from the combination + Offset

of pointer registers, the Instruction

Memory address
Pointer (IP), and immediate values

Examples

CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction address 3 8 A B 4 Stack address 5 F F E 0

DS 1 2 3 4 0
DI + 0 0 2 2
Data address 1 2 3 6 2
Microprocessor System Design 3-13
 Fetching Instructions
Where to fetch the next instruction?
8088 Memory

CS 1 2 3 4
IP 0012 12352 MOV AL, 0

12352

Update IP
Ͷ After an instruction is fetched, Register IP is updated as follows:








 
 



Ͷ For Example: the length of 78* is 2 bytes. After fetching this instruction,
the IP is updated to 0014

Microprocessor System Design 3-14