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David Harris

Harvey Mudd College
Spring 2004

 
’ À Brief History
’ CMOS Gate Design
’ Pass Transistors
’ CMOS Latches & Flip-Flops
’ Standard Cell Layouts
’ Stick Diagrams 

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lower in power! ± Revolutionary effects on society a    a  . À ’ R  First integrated circuit ± Flip-flop using two transistors ± Built by Jack Kilby at Texas Instruments ’ 2003 ± Intel Pentium 4 £processor ( million transistors) ± R2 Mbit DRÀM (> 0. billion transistors) ’ 3% compound annual growth rate over 4 years ± No other technology has grown so fast so long ’ Driven by miniaturization of transistors ± Smaller is cheaper. faster.

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 ’ R0R transistors manufactured in 2003 ± R00 million for every human on the planet Global Semiconductor Billings 200 (Billions of US$) R0 R00 0 0 R 2 R 4 R  R  R 0 R 2 R 4 R  R  2000 2002 Year a    a  .

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expensive. power-hungry. Hoddeson a    a  . unreliable ’ R 47 first point contact transistor ± John Bardeen and Walter Brattain at Bell Labs ± Read a  by Riordan.|     ’ uacuum tubes ruled in first half of 20th century Large.

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  ’ Bipolar transistors ± npn or pnp silicon structure ± Small current into very thin base layer controls large currents between emitter and collector ± Base currents limit integration density ’ Metal Oxide Semiconductor Field Effect Transistors ± nMOS and pMOS MOSFETS ± uoltage applied to insulated gate controls current between source and drain ± Low power allows very high integration a    a  .

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|   ’ R 70¶s processes usually had only nMOS transistors ± Inexpensive. but consume power while idle Intel RR0R 2-bit SRÀM Intel 4004 4-bit £Proc ’ R 0s-present CMOS processes for low idle power a    a  .

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 R.. ..  ! ’ R  Gordon Moore plotted transistor on each chip ± Fit straight line on semilog scale ± Transistor counts have doubled every 2 months R..

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 8 8  R.   8 8  R0. 8 28  R000 gates 8 8 R. Intel 8 R.000 gates R  R  R 8 R 8 R  R  2  > R0k gates Year a    a  ... entium II entium ro  R0 gates Transistors entium Intel 8 R.  entium entium III R.

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 ’ Many other factors grow exponentially ± Ex clock frequency. processor performance R0.000 R.000 4004 00 00 Clock Speed (MHz) R00 0 02 Intel3 R0 Intel4 Pentium Pentium Pro/II/III R Pentium 4 R 70 R 7 R 0 R  R 0 R  2000 200 Year a    a  .

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" ’ Àctivity ± Sketch a 4-input CMOS NÀND gate a    a  .

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" ’ Àctivity ± Sketch a 4-input CMOS NOR gate À B C D Y a    a  .

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’ Complementary CMOS logic gates ± nMOS pu .

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 pMOS pull-up ± pMOS pu up  .

a.  network inputs ± a.k. static CMOS output nMOS pull-down network Pull-up OFF Pull-up ON Pull-down OFF Z (float) R Pull-down ON 0 X (crowbar) a    a  .

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 $ a a a a ’ nMOS R = ON gR a 0 0 R R g2 ’ pMOS 0 = ON b 0 b R b 0 b R b (a) OFF OFF OFF ON ’    both must be ON a a a a a ’    either can be ON gR g2 0 0 0 R R 0 R R b b b b b (b) ON OFF OFF OFF a a a a a gR g2 0 0 0 R R 0 R R b b b b b (c) OFF ON ON ON a a a a a gR g2 0 0 0 R R 0 R R b b b b b (d) ON ON ON OFF a    a  .

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   ##  ’ Complementary CMOS gates always produce 0 or R ’ Ex NÀND gate ± Series nMOS Y=0 when both inputs are R ± Thus Y=R when either input is 0 ± Requires parallel pMOS Y À B ’ Rule of a.

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p   ± Pull-up network is complement of pull-down ± Parallel -> series. series -> parallel a    a  .

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# " ’ a.

p.

u   can do any inverting function ’ Ex   ‰ á  á ÷   ÷.

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À  À    ( ) ( )   À   À (c) ( )   À À Y Y  À    (f) ( ) a    a  .

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 # %À| ’   ‰Ë   á a    a  .

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 # %À| ’   ‰Ë   á À   Y  À  a    a  .

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  ’   of signal ± How close it approximates ideal voltage source ’ uDD and GND rails are strongest R and 0 ’ nMOS pass strong 0 ± But degraded or weak R ’ pMOS pass strong R ± But degraded or weak 0 ’ Thus nMOS are best for pull-down network a    a  .

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$  ’ Transistors can be used as switches s d s d a    a  .

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$  ’ Transistors can be used as switches  In ut 1 ut ut s d  stron  s d 1 1 s d 1 de raded 1  In ut ut ut  s d  de raded  s d 1   s d stron 1 a    a  .

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 # " ’ Pass transistors produce degraded outputs ’ 3 .

  pass both 0 and R well a    a  .

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 # " ’ Pass transistors produce degraded outputs ’ 3 .

gb = 0 g a b 0 strong 0 a b g = R. gb = R g = R. gb = 0 a b R strong R gb g g g a b a b a b gb gb gb a    a  .  pass both 0 and R well Input Output g = 0. gb = 0 g = R.

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 ’ 3  uff produces Z when not enabled EN EN À Y 0 0 À Y 0 R R 0 EN R R À Y EN a    a  .

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 ’ 3  uff produces Z when not enabled EN EN À Y 0 0 Z À Y 0 R Z R 0 0 EN R R R À Y EN a    a  .

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D   ’ Transmission gate acts as tristate buffer ± Only two transistors ± But .

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  Noise on À is passed on to Y N À Y N a    a  .

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|  ’ Tristate inverter produces restored output ± uiolates conduction complement rule ± Because we want a Z output À EN Y EN a    a  .

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|  ’ Tristate inverter produces restored output ± uiolates conduction complement rule ± Because we want a Z output À À À EN Y Y Y EN EN = 0 EN = R Y = 'Z' Y=À a    a  .

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  ’ 2R up  chooses between two inputs S S DR D0 Y 0 X 0 D0 0 0 X R Y DR R R 0 X R R X a    a  .

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  ’ 2R multiplexer chooses between two inputs S S DR D0 Y 0 X 0 0 D0 0 0 X R R Y DR R R 0 X 0 R R X R a    a  .

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"&   ’   ‰ R  ÷ ÷÷ ’ How many transistors are needed? a    a  .

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"&   ’   ‰ R  ÷ ÷÷ ’ How many transistors are needed? 20 DR S Y D0 DR 4 2 S 4 2 Y D0 4 2 2 a    a  .

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 # "  ’ Nonrestoring mux uses two transmission gates a    a  .

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 # "  ’ Nonrestoring mux uses two transmission gates ± Only 4 transistors S D0 S Y DR S a    a  .

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|    ’ Inverting multiplexer ± Use compound ÀOI22 ± Or pair of tristate inverters ± Essentially the same thing ’ Noninverting multiplexer adds an inverter D0 S D0 DR S S DR S S Y Y D0 0 S S S S Y DR R a    a  .

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=   ’ 4R mux chooses one of 4 inputs using two selects a    a  .

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=   ’ 4R mux chooses one of 4 inputs using two selects ± Two levels of 2R muxes ± Or four tristates SRS0 SRS0 SRS0 SRS0 D0 S0 SR D0 0 DR DR R 0 Y Y R D2 0 D2 D3 R D3 a    a  .

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the latch is . latch is  p  ± D flows through to Q like a buffer ’ When CLK = 0.  ’ When CLK = R.

 p c or      c    tc    a    a  .k.pu ± Q holds its old value independent of D ’ a.a.

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 ’ Multiplexer chooses D or old Q CLK CLK D Q Q R Q D Q 0 CLK CLK CLK a    a  .

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  Q Q D Q D Q CLK = R CLK = 0 CLK D Q a    a  .

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Q holds its value ’ a. p.k. D is copied to Q ’ Àt all other times.a. '& ’ When CLK rises.

     fp f.

   fp f.p.

p      l  a    a  .

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'& ’ Built from master and slave D latches     D       atch atch  D    a    a  .

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'&  QM Q D CLK = 0 QM D Q CLK = R CLK D Q a    a  .

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è   ’ Back-to-back flops can malfunction from clock skew ± Second flip-flop fires late ± Sees first flip-flop change and captures its result ± Called .

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 CLKR CLKR CLK2 CLK2 QR Flop Flop QR Q2 D Q2 a    a  .

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D   ( ’ Nonoverlapping clocks can prevent races ± Às long as nonoverlap exceeds clock skew ’ We will use them in this class for safe design ± Industry manages skew more carefully instead G G1    G G G1 G1 G G1 G1 G a    a  .

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" ’ Layout can be very time consuming ± Design gates to fit together nicely ± Build a library of standard cells ’ Standard cell design methodology ± uDD and GND should abut (standard height) ± Àdjacent gates should satisfy design rules ± nMOS at bottom and pMOS at top ± Àll gates include well and substrate contacts a    a  .

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 #DÀD% ’ Horizontal N-diffusion and p-diffusion strips ’ uertical polysilicon gates ’ MetalR uDD rail at top ’ MetalR GND rail at bottom ’ 32  by 40  a    a  .

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(# ’ c   help plan layout quickly ± Need not be to scale ± Draw with color pencils or dry-erase markers a    a  .

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ü ( ’ À   c is the space required for a wire ± 4  width. 4  spacing from neighbor =   pitch ’ Transistors also consume one wiring track a    a  .

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ü  ’ Wells must surround transistors by   ± Implies R2  between opposite transistor flavors ± Leaves room for one wire track a    a  .

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À# ’ Estimate area by counting wiring tracks ± Multiply by  to express in  a    a  .

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 # %À| ’ Sketch a stick diagram for O3ÀI and estimate area ±   ‰Ë á a    a  .

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 # %À| ’ Sketch a stick diagram for O3ÀI and estimate area ±   ‰Ë á a    a  .

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 # %À| ’ Sketch a stick diagram for O3ÀI and estimate area ±   ‰Ë á a    a  .

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