8085 Microprocessor:

Architecture & Support Components

Contents
n Pin diagram of 8085 n 8085 Operations n Architecture of 8085 n 8085 Communication with Memory

Pinout Diagram of 8085

U 7

n A 40-pin IC n Six groups of signals n Address Bus n Data Bus n Control and Status pins n Power Supply & frequency signals n Externally initiated Signals n Serial I/O ports

1 1 1 1 1 1 1 1 1 1 2

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0

X1 X2 R ST-O T SO D S ID TR AP R S T 7 .5 R S T 6 .5 R S T 5 .5 IN T R IN T A AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 VSS

VC C H O LD H LD A C LKO R S T - IN R EAD Y IO /M S1 R D W R ALE S0 A15 A14 A13 A12 A11 A10 A9 A8

4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2

0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1

8085

Logic Pinout of 8085

VC C VSS S ID SO D TR AP R S T 5 .5 R S T 6 .5 R S T 7 .5 IN T R H O LD R EAD Y R S T - IN IN T A H LD A R ST -O T C LKO 8085

Serial I/O ports Externally initiated signals

5 4 6 9 8 7 10 39 35 36 11 38 3 37

Control & Status

ALE W R R D IO /M S0 S1

3 3 3 3 2 3

0 1 2 4 9 3

Control & Status

Address Bus

Power Supply & frequency

40 20

Data Bus

1 2

U 8 X1 X2 AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 A8 A9 A10 A11 A12 A13 A14 A15

1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2

2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8

8085 Operations
n Microprocessor Initiated Operations n Internal Operations n Peripheral/Externally Initiated Operations

Microprocessor Initiated Operations

n Memory Read n Memory Write n I/O Read n I/O Write

Internal Operations
n Store 8-bit data n Perform Arithmetic and Logic Operations n Test for conditions n Sequence the execution of instructions n Store/Retrieve data from stack during

execution

Peripheral/Externally Initiated Operations

n Reset n Interrupt n Ready n Hold

Architecture of 8085
n Power Supply a +5V DC power supply n Maximum clock frequency of 3MHz n 8-bit general purpose microprocessor n 16-bit Address Bus
n

Capable of addressing 64K of memory

Architecture of 8085

Architecture 0f 8085 Cont

n ALU n Timing and Control Unit n General Purpose n n n n n Interrupt Control n Serial I/O Control n Address Bus n Data Bus

Registers Program Status word Program Counter Stack Pointer Instruction Register and Decoder
n n

Architecture 0f 8085 Cont

n Arithmetic Logic Unit (ALU) n 8085 has 8-bit ALU n Performs arithmetic & Logic operations on data n Timing & Control Unit
n

Generates timing and control signals

n General Purpose Registers n 8-bit registers (B,C,D,E,H,L) n 16-bit register pairs (BC, DE, HL,PSW) n

Architecture 0f 8085 Cont

n Program Status Word (PSW) n Accumulator and Flag Register can be combined as a register pair called PSW n Instruction Register and Decoder

Instruction fetched from memory is stored in Instruction register (8-bit register) n Decoder decodes the instruction and directs the Timing & Control Unit accordingly
n

Architecture 0f 8085 Cont

n Interrupt Control n 8085 has 5 interrupt signals
n n n n n

INTR general purpose interrupt RST 5.5 Restart Interrupts RST 6.5 RST 7.5 TRAP non-maskable interrupt

The interrupts listed above are in increasing order of priority

n

Architecture 0f 8085 Cont

n Serial I/O Control n 8085 has two signals for serial communication n SID Serial Input Data n SOD Serial Output Data

Architecture 0f 8085 Cont

n Address Bus n Used to address memory & I/O devices n 8085 has a 16-bit address bus
Higher-order Address Lower-order Address

A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Data Bus

nData Bus nUsed to transfer instructions and data n8085 has a 8-bit data bus

8085 Communication with Memory

n Involves the following three steps 1.Identify the memory location (with address) 2.Generate Timing & Control signals 3.Data transfer takes place

Example: Memory Read Operation

3 2

Timing Diagram

Demultiplexing Address/Data Bus

n 8085 identifies a memory location with its 16

address lines, (AD0 to AD7) & (A8 to A15) n 8085 performs data transfer using its data lines, AD0 to AD7 n Lower order address bus & Data bus are multiplexed on same lines i.e. AD0 to AD7. n Demultiplexing refers to separating Address & Data signals for read/write operations
n

Need for Demultiplexing

RD

A8-A15
20H

AD0-AD7 8085
05H

Memory
4FH 2005H

Need for Demultiplexing

n The 16-bit address of the memory location

must be applied to the memory chip for the whole duration of the memory read/write operation. n Lower-order address needs to be saved before microprocessor uses it for data transfer

8085 Interfacing with Memory chips

Address Address

8085

Data

Memory Interface

Data

Memory Chip

Control

Control

8085 Interfacing with Memory chips

Data

8085

74LS373 AD0-AD7 ALE A8-A15 Control A8-A15 A0 A7

Memory Chip

Memory Interface

8085 Interfacing with Memory chips

Data

8085

74LS373 AD0-AD7 ALE A8-A15 IO/M RD A8-A15 A0 A7

Program Memory
CS RD

Memory Interface

U 3 36 1 2 5 6 9 8 7 1 1 2 3 3 3 3 0 1 9 3 9 5 8 4 37 3 U 1 R S T - IN X1 X2 S ID TR AP R S T 5 .5 R S T 6 .5 R S T 7 .5 IN T R IN T A S0 S1 H O LD R EAD Y H LD A SO D C LKO R ST -O T 8085 31 WR AD AD AD AD AD AD AD AD AL A A A1 A1 A1 A1 A1 A1 IO /M R D 0 1 2 3 4 5 6 7 E 8 9 0 1 2 3 4 5 1 1 1 1 1 1 1 1 3 2 2 2 2 2 2 2 2 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 3 4 7 8 3 4 7 8 1 U 2 D D D D D D D D G 0 1 2 3 4 5 6 7 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 O C 2 5 6 9 1 1 1 1 1 10 9 8 7 6 5 4 3 A0 A1 A2 A3 A4 A5 A6 A7 1 1 1 1 1 1 1 1 1 2 3 5 6 7 8 9

1 1 1 1 1

2 5 6 9

O O O O O O O O

0 1 2 3 4 5 6 7

74LS373

2 2 2 2

5 4 1 3 2 26 27 1 20 22

A8 A9 A1 A1 A1 A1 A1 A1 C E

0 1 2 3 4 5

34 32

O E /V P P

27C 512A

Memory Mapping
n 8085 has 16-bit Address Bus n The complete address space is thus given by

the range of addresses 0000H FFFFH n The range of addresses allocated to a memory device is known as its memory map

Memory map: 64K memory device

n Address lines required: 16 (A0 A15) n Memory map: 0000H - FFFFH

Memory map: 32K memory device

nAddress lines required: 15 (A0 A14) nMemory map: depends on how address line

A15 is connected

36 1 2 5 6 9 8 7 1 1 2 3 3 3 3 0 1 9 3 9 5 8 4 37 3

U 1 R S T - IN X1 X2 S ID TR AP R S T 5 .5 R S T 6 .5 R S T 7 .5 IN T R IN T A S0 S1 H O LD R EAD Y H LD A SO D C LKO R ST -O T 8085 31 WR AD AD AD AD AD AD AD AD AL 0 1 2 3 4 5 6 7 E

1 1 1 1 1 1 1 1 3 2 2 2 2 2 2 2

2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 U 5A 3 74LS32

3 4 7 8 13 14 17 18 11

U 2 D D D D D D D D G 0 1 2 3 4 5 6 7 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 O C

2 5 6 9 1 1 1 1 1

2 5 6 9

10 9 8 7 6 5 4 3

U 4 A A A A A A A A 0 1 2 3 4 5 6 7 O O O O O O O O 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 1 2 3 5 6 7 8 9

74LS373

A8 A9 A10 A11 A12 A13 A14 A15 IO /M R D

2 2 2 2

5 4 1 3 2 26 27 20 22 1

A A A A A A A

8 9 1 1 1 1 1

0 1 2 3 4

21 8 32 4 32

C E O E VPP 27C 256

Memory device is selected only if IO/M = 0 & A15 = 0

n So the memory map is

A15 A14 A13 A12 0 0 0 0
A11 to A0 0. 0 0

= 0000H to = 7FFFH

A15 A14 A13 A12

A11 to A0

1. 111

Interfacing I/O devices with 8085

Peripheral-mapped I/O & Memory-mapped I/O

Interfacing I/O devices with 8085

I/O Interface I/O Devices

8085

System Bus

Memory Interface

Memory Devices

Techniques for I/O Interfacing

n Memory-mapped I/O n Peripheral-mapped I/O

Memory-mapped I/O
n 8085 uses its 16-bit address bus to identify a

memory location n Memory address space: 0000H to FFFFH n 8085 needs to identify I/O devices also n I/O devices can be interfaced using addresses from memory space n 8085 treats such an I/O device as a memory location n This is called Memory-mapped I/O

Peripheral-mapped I/O
n 8085 has a separate 8-bit addressing scheme

for I/O devices n I/O address space: 00H to FFH n This is called Peripheral-mapped I/O or I/O-mapped I/O

8085 Communication with I/O devices

n Involves the following three steps 1.Identify the I/O device (with address) 2.Generate Timing & Control signals 3.Data transfer takes place n 8085 communicates with a I/O device only if

there is a Program Instruction to do so

1.

1.Identify the I/O device (with address)

1. Memory-mapped I/O (16-bit address) 2. Peripheral-mapped I/O (8-bit address)
n

2.Generate Timing & Control Signals

n Memory-mapped I/O n Reading Input: IO/M = 0, RD = 0 n Write to Output: IO/M = 0, WR = 0 n Peripheral-mapped I/O n Reading Input: IO/M = 1, RD = 0 n Write to Output: IO/M = 1, WR = 0
n

3. Data transfer takes place

8085 Communication with I/O devices

n Involves the following three steps Identify the I/O device (with address) Generate Timing & Control signals Data transfer takes place n 8085 communicates with a I/O device only if

there is a Program Instruction to do so

1.

Peripheral I/O Instructions

n IN Instruction n Inputs data from input device into the accumulator n It is a 2-byte instruction n Format: IN 8-bit port address n Example: IN 01H n

n OUT Instruction n Outputs the contents of accumulator to an output device n It is a 2-byte instruction n Format: OUT 8-bit port address n Example: OUT 02H

----------Example Program---------n WAP to read a number from input port (port

address 01H) and display it on ASCII display connected to output port (port address 02H) IN 01H ;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 OUT 02H ;display 3 on ASCII display

Memory-mapped I/O Instructions

n I/O devices are identified by 16-bit addresses n 8085 communicates with an I/O device as if it

were one of the memory locations n Memory related instructions are used n For e.g. LDA, STA n LDA 8000H
n

Loads A with data read from input device with 16-bit address 8000H

n STA 8001H n Stores (Outputs) contents of A to output device with 16-bit address 8001H

----------Example Program---------n WAP to read a number from input port (port

address 8000H) and display it on ASCII display connected to output port (port address 8001H) LDA 8000H;reads data value 03H (example)into ;accumulator, A = 03H MVI B, 30H;loads register B with 30H ADD B ;A = 33H, ASCII code for 3 STA 8001H;display 3 on ASCII display