Static and Dynamic Power in CMOS

Test
Dynamic and Static Power in CMOS

Vishwani D. Agrawal
Auburn University, USA
vagrawal@eng.auburn.edu
Srivaths Ravi
Texas Instruments India
Srivaths.ravi@ti.com
Hyderabad, July 30-31, 2007

http://www.eng.auburn.edu/~vagrawal/hyd.html
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2 1
Components of Power
Dynamic
Signal transitions

Logic activity Glitches
Short-circuit
Static
Leakage
Ptotal =
Pdyn + Pstat Ptran + Psc + Pstat

2
Copyright Agrawal & Srivaths, 2007
Low-Power Design and Test, Lecture 2
Power of a Transition: Ptran

Ron vi (t) R = large Ground VDD ic(t) vo(t) CL
Charging of a Capacitor
R t=0 V Charge on capacitor, q(t) Current, i(t)
i(t)
v(t) C = = C v(t) C dv(t)/dt

4
dq(t)/dt
i(t)
C dv(t)/dt = [V v(t)] /R dv(t) V v(t) = dt RC dv(t) dt = V v(t) RC -t ln [V v(t)] = + A RC
Initial condition, t = 0, v(t) = 0 A = ln V -t v(t) = V [1 exp()] RC

v(t) =
-t V [1 exp( )] RC = V -t exp( ) R RC
i(t)
dv(t) C dt
Total Energy Per Charging Transition from Power Supply

V i(t) dt =
0
Etrans = =
V2 -t exp( ) dt 0 R RC
CV2
Energy Dissipated per Transition in Resistance

2 R i (t) dt
0
= =
V2 -2t R exp( ) dt R2 0 RC 1 CV2 2
Energy Stored in Charged Capacitor

-t V -t v(t) i(t) dt = V [1-exp( )] exp( ) dt 0 0 RC R RC 1 = CV2 2
Transition Power
Gate output rising transition

Energy dissipated in pMOS transistor = CV 2/2 Energy stored in capacitor = CV 2/2
Gate output falling transition

Energy dissipated in nMOS transistor = CV 2/2
Energy dissipated per transition = CV 2/2 Power dissipation:
Ptrans =
Etrans fck = =
fck CV2/2
activity factor
Low-Power Design and Test, Lecture 2 10
Components of Power
Dynamic
Signal transitions

Short-circuit
Static
Leakage
Ptotal =
Pdyn + Pstat Ptran + Psc + Pstat

11
Short Circuit Power of a Transition: Psc

VDD vi (t) isc (t) vo(t) CL Ground
12
Short Circuit Current, isc (t)

VD D VD D - VTp Vi (t) Volt
ptransistor starts conducting
Vo(t)
n-transistor cuts-off
VTn
Isc 0
isc (t)
Iscmxf a
tB
tE
Time (ns)
13
Peak Short Circuit Current
Increases with the size (or gain, ) of transistors Decreases with load capacitance, CL Largest when CL = 0 Reference: M. A. Ortega and J. Figueras, Short Circuit Power Modeling in Submicron CMOS, PATMOS 96, Aug. 1996, pp. 147-166.
Short-Circuit Energy per Transition
Escf = =
tB
tE
VDD isc (t)dt
(tE tB) Iscmxf VDD / 2 a = tf (VDD - |VTp | - VTn ) Iscmxf a = tr (VDD - |VTp | - VTn ) Iscmxr a /2 /2
Escf Escr
Escf = Escr = 0, when VDD = |VTp | + VTn

Short-Circuit Energy
Increases with rise and fall times of input Decreases for larger output load capacitance Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down
Short-Circuit Power Calculation

Assume equal rise and fall times Model input-output capacitive coupling (Miller capacitance) Use a spice model for transistors
T. Sakurai and A. Newton, Alpha-power Law MOSFET model and Its Application to a CMOS Inverter, IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.
Short Circuit Power
Psc
fck Esc
18
Psc , Rise Time and Capacitance

VD D
Ron vi (t)
VDD ic(t)+isc (t) vo(t)

vo(t)
tf
R = large Ground
CL
tr
vo(t) R
19
isc , Rise Time and Capacitance

-t VDD [1- exp()] vo(t) R(t) C = R(t) R(t)
Isc (t) =
20
iscmx , Rise Time and Capacitance a

i
Small C vo(t)
Large C vo(t) 1 R(t)
iscmx a
tf
t
Psc , Rise Times, Capacitance
For given input rise and fall times short circuit power decreases as output capacitance increases. Short circuit power increases with increase of input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.
Summary: Short-Circuit Power by each Short-circuit power is consumed
transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when VDD |Vtp | +Vtn .
Components of Power
Dynamic
Signal transitions

Short-circuit
Static
Leakage
24
Leakage Power
Ground
Source Gate
IG
VDD R
Drain
n+
Bulk Si (p)
IPT IG L ID
Isub
n+ ID
nMOS Transistor
25
Leakage Current Components Subthreshold conduction, I

sb u
Reverse bias pn junction conduction, ID Gate induced drain leakage, IG L due to ID tunneling at the gate-drain overlap Drain source punchthrough, IPT due to short channel and high drain-source voltage Gate tunneling, IG through thin oxide; may become significant with scaling
26
Subthreshold Current
Isub = 0 Cox (W/L) Vt2 exp{(VG VTH ) / nVt } S 0: carrier surface mobility Cox : gate oxide capacitance per unit area L: channel length W: gate width Vt = kT/q: thermal voltage n: a technology parameter
ID for Short Channel Device S

Isub = 0 Cox (W/L)Vt2 exp{(VG VTH + VDS )/nVt} S VDS = drain to source voltage : a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
28
Increased Subthreshold Leakage

Scaled device
Log (Drain current)
Ic
Isub
0 VTH VTH Gate voltage
29
Summary: Leakage Power

Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Multiple-threshold devices are used to reduce leakage power.
30
Technology Scaling
Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies Constant electric field assumed
31
Constant Electric Field Scaling

B. Davari, R. H. Dennard and G. G. Shahidi, CMOS Scaling for High Performance and Low PowerThe Next Ten Years, Proc. IEEE, April 1995, pp. 595-606. Other forms of scaling are referred to as constant-voltage and quasiconstant-voltage.
Bulk nMOSFET
Polysilicon Gate Source n+ L p-type body (bulk) SiO2 Thickness = tox
W n+
Drain
Technology Scaling

A scaling factor (S ) reduces device dimensions as 1/S. Successive generations of technology have used a scaling S = 2, doubling the number of transistors per unit area. This produced 0.25, 0.18, 0.13, 90nm and 65nm technologies, continuing on to 45nm and 30nm. A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston: Pearson Addison-Wesley, 2005, Section 4.9.1.
Constant Electric Field Scaling

Device Parameter Length, L Width, W Gate oxide thickness, tox Supply voltage, VDD Threshold voltages, Vtn , Vtp Substrate doping, NA
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2
Scaling 1/S 1/S 1/S 1/S 1/S S

35
Constant Electric Field Scaling (Cont.) Device Characteristic Scaling

Current, Ids Resistance, R Gate capacitance, C Gate delay, Clock frequency, f Dynamic power per gate, P Chip area, A Power density Current density
Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 2
W / (L tox ) (VDD Vt ) VDD / Ids W L / tox RC 1/ CV 2 f P/A Ids /A
S 1/S 1 1/S 1/S S 1/S 1/S 1 S

36
2 2
Problem: A Design Example
A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. Compare two power reduction strategies for extending the battery life:
A. B. Clock frequency is reduced to half, keeping all other parameters constant. Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.
Solution: Part A. Clock Frequency Reduction
Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Energy consumption for the task will be, Energy = (P / 2 + P ) 2T = 3PT which is greater than the original 2PT.
38
Solution: Part B. Supply Voltage Reduction
When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is, Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.
39

Static and Dynamic Power in CMOS

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Dynamic and Static Power in CMOS

Hyderabad, July 30-31, 2007

Logic activity Glitches

Pdyn + Pstat Ptran + Psc + Pstat

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Power of a Transition: Ptran

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

v(t) C = = C v(t) C dv(t)/dt

C dv(t)/dt = [V v(t)] /R dv(t) V v(t) = dt RC dv(t) dt = V v(t) RC -t ln [V v(t)] = + A RC

Initial condition, t = 0, v(t) = 0 A = ln V -t v(t) = V [1 exp()] RC

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Total Energy Per Charging Transition from Power Supply

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Energy Dissipated per Transition in Resistance

V2 -2t R exp( ) dt R2 0 RC 1 CV2 2

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Energy Stored in Charged Capacitor

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Gate output rising transition

Gate output falling transition

Energy dissipated per transition = CV 2/2 Power dissipation:

Logic activity Glitches

Pdyn + Pstat Ptran + Psc + Pstat

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Short Circuit Power of a Transition: Psc

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Short Circuit Current, isc (t)

Copyright Agrawal & Srivaths, 2007

Peak Short Circuit Current

Copyright Agrawal & Srivaths, 2007

Short-Circuit Energy per Transition

VDD isc (t)dt

Escf = Escr = 0, when VDD = |VTp | + VTn

Copyright Agrawal & Srivaths, 2007

Short-Circuit Power Calculation

Short Circuit Power

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

Psc , Rise Time and Capacitance

VDD ic(t)+isc (t) vo(t)

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

isc , Rise Time and Capacitance

Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test, Lecture 2

iscmx , Rise Time and Capacitance a

Large C vo(t) 1 R(t)

Copyright Agrawal & Srivaths, 2007

Psc , Rise Times, Capacitance

Copyright Agrawal & Srivaths, 2007

Summary: Short-Circuit Power by each Short-circuit power is consumed

Copyright Agrawal & Srivaths, 2007

Logic activity Glitches

Copyright Agrawal & Srivaths, 2007