CMOS FABRICATION

Technology

T.khadar 9949943802

 CMOS process: The following discussion will concentrate on the well established CMOS fabrication ,which requires that both n-channel (n-MOS) and p-channel (p-MOS) transistors built on the same chip

 CMOS processes:
-> P-well process ->N-well process ->Twin-tub ->Silicon-on-insulator

 Electrical properties of MOS and BICMOS circuits: ->CMOS inverter

P-well:
The substrate is N-Type. The NChannel device is built into a PType well within the parent N-Type substrate. The P-channel device is built directly on the substrate.

P-well on N-substrate Steps : ->N-type substrate

->Oxidation, and mask (MASK 1) to create Pwell (4-5Qm deep) ->P-well doping P-well acts as substrate for n-MOS devices. The two areas are electrically isolated using thick sio2 field oxide Steps

P-well N-type substrate

4-5 Qm

Polysilicon gate formation

Grow thick field oxide Pattern (MASK 2) to expose n-MOS and p-MOS active regions Remove p-well definition oxide Grow thin layer of SiO2 (~0.1Qm) gate oxide, over the entire chip surface Deposit polysilicon on top of gate oxide to form gate structure Pattern poly on gate oxide (MASK 3)

Polysilicon gate formation

Thin gate oxide (SiO2)

Gate (patterned polysilicon on thin oxide)

Thick field oxide

N-MOS active region

P-MOS active region N-type substrate

N-MOS P+ Source/Drain diffusion

->Implant P+ n-MOS S/D regions (MASK 4)
P+ implant/diffusion

P+ mask Thick field oxide N-type substrate

P-MOS p+ source/drain diffusion

->Implant N+ p-MOS S/D regions -> (MASK 5 often the inverse of MASK 4)

N+ implant/diffusion N+ mask

P+ N-type substrate

N+

P-MOS N+ source/drain diffusion , contact holes and metalization

->Oxide and pattern for contact holes (MASK 6) ->Deposit metal and pattern (MASK 7) ->Passivation oxide and pattern bonding pads (MASK 8) ->P-well acts as substrate for n-MOS devices. ->Two separate substrates : requires two separate substrate connections ->Definition of substrate connection areas can be included in MASK 4/MASK5

CMOS P-well process

N+(for NSubstrate Contact)

Vdd

Vout

Vss

P+ (for Psubstrate contact)

P P+
P channel Device

N+

N channel Device

N-type substrate

CMOS fabrication process overview

Disadvantages of P-well
->High power consumption ->low perfomance ->easy latch-up ->Does not support high system realiblity

CMOS N-well process

N-Well: The base wafer is of lightly doped P type, a well mask is used to diffuse in N-type wells where the P-channel devices will be fabricated.

Main steps in a typical n-well process

CMOS N-well process

Vin P+ for P-substrate Vdd contact) Vout Vss N+ (for Nsubstrate contact)

N+

N channel Device

P+

N-well
P channel Device

P-type substrate

Disadvantages of N-well
->High power consumption ->low perfomance ->easy latch-up ->Does not support high system realiblity

Twin-Tub Twin-tub: The base wafer is very weakly doped

and with two separate masks wells of both P type and N type material are constructed where N-channel and P-channel devices respectively will be fabricated.
Process sequence : a. Tub formation b. Thin-Oxide construction c. Source & drain implantations d. Contact cut definition e. Metallization

Starting material: an n+ or p+ substrate with lightly doped "epitaxial" or "epi" layer -> to protect "latch up" B. Epitaxy" a. Grow high-purity silicon layers of controlled thickness b. With accurately determined dopant concentrations c. Electrical properties are determined by the dopant and its

Disadvantages of Twin well process

-> expensive ->extra processing steps ->But n-mos and p-mos devices can be optimised seperastly ->Also , insulating substrate gives latch-up immunity

silicon on insulator ->SOI is a semiconductor fabrication

techinque developed by IBM that uses pure crystal silicon oxide for integrated circuts and microchips

-> It is a processes of placing a thin layer

of silicon on top of an insulating material in order to decrease the parastic capacitance hence speed up the perfomance

Silicon on insulator
SOI: soi allows the creation of independent ,completely isolated N-MOS and P-MOS transistors virtually side-by-side on an insulating substrate

Steps in typical SOI CMOS: process

steps used in a typical SOI CMOS

Advantages of SOI: -> suitable for high-energy radiation ->

enviormentS

parasitic capacitance of SOI devices are much smaller

->

No latch up

-> High device density

->Major bottleneck is high manufacturing costs of the wafer. ->Floating-body effects impede extensive usage of SOI. ->Device integration surface. dopant reaction with the oxide

Disadvantages of SOI

->Electrical differences between and SOI nad bulk devices.

CMOS inverter
->An inverter is the simplest logic gate which implements the logic operation of negation . A logic symbol and the truth I /operation table V
IN OUT VIN VOUT 0 1 VL VH 1 0 VH VL
P-mos

Y
N-mos

CMOS Inverter Characteristics

No current flow for either logical 1 or logical 0 inputs Full logical 1 and 0 levels are presented at the output For devices of similar dimensions the p channel is slower than the n channel device

Uses of CMOS inverter:

->Many people don't give a moments thought to the CMOS inverter in their digital camera. ->However, this is actually a very clever piece of technology which is used to convert light into electrons, which can then be stored on digital memory cards. ->The CMOS Inverter is an integral part of your camera, as without it you would be unable to capture anything.

CMOS inverter
Condition 1:
A 0 1 0 Y

OFF
A=1 Y=0

ON
A Y

GND

Condition 2:

A 0 1

Y 1 0

VDD ON
A=0 Y=1

OFF
A Y

GND

CMOS NAND Gate

Condition 1:

A 0 0 1 1

B 0 1 0 1

Y 1

ON A=0 B=0

ON Y=1 OFF OFF

Condition 2:

OFF
A 0 0 1 1 B 0 1 0 1 Y 1 1

A=0 B=1

ON Y=1 OFF ON

Condition 3:

O N
A 0 0 1 1 B 0 1 0 1 Y 1 1 1

OF F Y1 = O N OF F

A1 = B0 =

Condition 4:

FF
A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0

FF Y=0 N N

A=1 B=1

CMOS inverters have several important advantages:

For example, CMOS inverters only use electricity when they are turned on and off, resulting in very little power consumption. Consequently, CMOS inverters produce very little heat waste, making them highly efficient and usable in a wide variety of small, delicate electronic devices. Additionally, CMOS inverters have high noise immunity, which allows them to block both incoming and outgoing frequency spikes. Finally, CMOS inverters are inexpensive to mass produce

Thank you