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Barrel Shifter
Combinational logic circuit with n data inputs, n data outputs and a set of
control inputs
Control i/ps specify how to shift the data between input and output
Part of p CPU that specifies the direction of shift(left or right), type of shift
Shift operation is controlled by 6 bits: Four bits for the length, one bit for
Cont..
The 2 main blocks of barrel shifter are: shift-and-rotate array (SARA) and
SARA performs the actual shift-and-rotate task on available data while its
SARA occupies most of the chip area, determines the critical path delay of
SARA
For a 16 bit barrel shifter, SARA is designed using 5 stages each with
sixteen cells
Basic cell used in this array is an AO22 gate that is called q-mux
Ci1,Ci2 come for control logic and In1,In2 come from external inputs or previous stage o/ps
D3L Logic
Uses local data instead of a global clock to maintain correct pre-charge and
evaluation phases
Eliminating the clock from dynamic gates using D3L logic yields less power
Low power consumption and faster gate operation are advantages of D3L
logic
SARA Implementation
Elimination of clk signal is done by substitution of suitable input combinations
Control logic o/ps are set low in pre-charge phase to charge the entire circuit
When the condition In1=In2=0 is satisfied , each qmux cell is pre-charged and
consumption
vhdl coding
16 bit barrel shifter is implemented using behavioral model through modelsim
Inputs to the barrel shifter are a 16 bit input, 4 bit control input whose decimal
eq gives no of bits of shift or rotate(0000-1111) , 3 bit opsel indicates type of operation and a carry bit
Finally, We get 16 bit output after shift or rotate and an o/p carry bit
Simulations
For 2 bits shift or rotate:
Let, 16 bit input (a) = 1011001011000101; 4 bit control i/p (b)= 0010 ; opsel =000,010,100,110 ; c_in= 0
Indicates the operations of logical shift left, arithmetic shift left, rotate left