Evolution in

Complexity
Evolution in Transistor
Count
Evolution in Speed/Performance
Intel 4004 Micro-
Processor
Intel Pentium (II)
microprocessor
Design Abstraction Levels
n+ n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Silicon in 2010
Die Area: 2.5x2.5 cm
Voltage: 0.6 V
Technology: 0.07 m
Density Access Time
(Gbits/cm2) (ns)
DRAM 8.5 10
DRAM (Logic) 2.5 10
SRAM (Cache) 0.3 1.5
Density Max. Ave. Power Clock Rate
(Mgates/cm2) (W/cm2) (GHz)
Custom 25 54 3
Std. Cell 10 27 1.5
Gate Array 5 18 1
Single-Mask GA 2.5 12.5 0.7
FPGA 0.4 4.5 0.25
Jan M. Rabaey
The Devices
The MOS Transistor
n+ n+
p-substrate
Field-Oxyde
(SiO
2
)
p+ stopper
Polysilicon
Gate Oxyde
Drain
Source
Gate
Bulk Contact
CROSS-SECTION of NMOS Transistor
Current-Voltage Relations
Dynamic Behavior of MOS Transistor
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
THE INVERTERS
DIGITAL GATES
Fundamental Parameters
Functionality
Reliability, Robustness
Area
Performance
Speed (delay)
Power Consumption
Energy
The CMOS Inverter:
A First Glance
V
DD
V
in
V
out
C
L
VTC of Real Inverter
0.0 1.0 2.0 3.0 4.0 5.0
V
in
(V)
1.0
2.0
3.0
4.0
5.0
V
o
u
t

(
V
)
V
M
NM
H
NM
L
Delay Definitions
t
pHL
t
pLH
t
t
V
in
V
out
50%
50%
t
r
10%
90%
t
f
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
C
db2
C
db1
C
gd12
C
w
C
g4
C
g3
V
out2
Fanout
Interconnect
V
out
V
in
C
L
Simplified
Model
CMOS Inverters
Polysilicon
In
Out
Metal1
V
DD
GND
PMOS
NMOS
1.2 m
=2

Scaling Relationships for Long Channel Devices
COMBINATIONAL
LOGIC
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Static CMOS
V
DD
V
SS
PUN
PDN
In1
In2
In3
F = G
In
1
In
2
In
3
PUN and PDN are Dual Networks
PMOS Only
NMOS Only
Example Gate: NAND
Transistor Sizing
V
DD
A
B
C
D
D
A
B C
1
2
2
2
6
6
12
12
F
for symmetrical response (dc, ac)
for performance
Focus on worst-case
Input Dependent
4-input NAND Gate
Out
In
1
In
2
In
3
In
4
In
3
In
1
In
2
In
4
In
1
In
2
In
3
In
4
V
DD
Out
GND
V
DD
In1 In2 In3 In4
Vdd
GND
Out
Ratioed Logic
V
DD
V
SS
PDN
In
1
In
2
In
3
F
R
L
Load
V
DD
V
SS
In
1
In
2
In
3
F
V
DD
V
SS
PDN
In
1
In
2
In
3
F
V
SS
PDN
Resistive
Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
V
T
< 0
Goal: to reduce the number of devices over complementary CMOS
Pseudo-NMOS
V
DD
A B C D
F
C
L
V
OH
= V
DD
(similar to complementary CMOS)
k
n
V
DD
V
Tn

( )
V
OL
V
OL
2
2
-------------
\ .
|
| |
k
p
2
------ V
DD
V
Tp

( )
2
=
V
OL
V
DD
V
T

( )
1 1
k
p
k
n
------ (assuming that V
T
V
Tn
V
Tp
) = = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
Dynamic Logic
M
p
M
e
V
DD
PDN
|
In
1
In
2
In
3
Out
M
e
M
p
V
DD
PUN
|
In
1
In
2
In
3
|
|
Out
C
L
C
L
|
p network
|
n network
2 phase operation:
Evaluation
Precharge
Example
M
p
M
e
V
DD
|
Out
|
A
B
C
N + 1 Transistors
Ratioless
No Static Power Consumption
Noise Margins small (NM
L
)
Requires Clock
Cascading Dynamic Gates
M
p
M
e
V
DD
|
|
M
p
M
e
V
DD
|
|
In
Out1 Out2
|
Out2
Out1
In
V
t
A
V
V
Tn
(a)
(b)
Only 0

1 Transitions allowed at inputs!

Domino Logic
M
p
M
e
V
DD
PDN
|
In
1
In
2
In
3
Out1
|
M
p
M
e
V
DD
PDN
|
In
4
|
Out2
M
r
V
DD
Static Inverter
with Level Restorer
Where Does Power Go in CMOS?
Dynamic Power Consumption
Short Circuit Currents
Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
SEQUENTIAL LOGIC
Master-Slave Flip-Flop
S
R
Q
Q Q
Q
S
R
Q
Q
J
K
|
MASTER SLAVE
Q
J
K
Q
|
PRESET
CLEAR
SI
RI
CMOS Clocked SR- FlipFlop
V
DD
Q
Q
R S
| |
M1
M3
M4 M2
M6
M5 M7
M8
2 phase non-overlapping clocks
|
2
|
1
|
1
|
2
D
In
|
1
|
2
t
|12
Pipelining
R
E
G
|
R
E
G
|
R
E
G
|
log
.
R
E
G
|
R
E
G
|
R
E
G
|
.
R
E
G
|
R
E
G
|
log
Out Out
a
b
a
b
Non-pipelined version
Pipelined version
Arithmetic Building
Blocks
A Generic Digital Processor
MEMORY
DATAPATH
CONTROL
I
N
P
U
T
-
O
U
T
P
U
T
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath ( adder , multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
Bit-Sliced Design
Bit 3
Bit 2
Bit 1
Bit 0
R
e
g
i
s
t
e
r
A
d
d
e
r
S
h
i
f
t
e
r
M
u
l
t
i
p
l
e
x
e
r
Control
D
a
t
a
-
I
n
D
a
t
a
-
O
u
t
Tile identical processing elements
Layout Strategies for Bit-Sliced
Datapaths
Well
Control
Wires
(M1)
Well
Wires
(M1)
GND
V
DD
GND
GND
V
DD
GND
Approach I
Signal and power lines parallel
Approach II
Signal and power lines perpendicular
S
i
g
n
a
l
s

W
i
r
e
s

(
M
2
)
S
i
g
n
a
l
s

W
i
r
e
s

(
M
2
)
Layout of Bit-sliced Datapaths
COPING WITH
INTERCONNECT
Impact of Interconnect Parasitics
Reduce Reliability
Affect Performance
Classes of Parasitics
Capacitive
Resistive
Inductive
Using Cascaded Buffers
C
2
C
1
C
i
C
L
1
u u
2
u
N-1
In Out
u
opt
= e
ISSUES IN TIMING
The Ellmore Delay
The Clock Skew Problem
CL1 R1 CL2 R2 CL3 R3
In Out
|
t
|
t
|
t
|
t
l,min
t
l,max
t
r,min
t
r,max
t
i
Clock Edge Timing Depends upon Position
Clock Rates as High as 500 Mhz in CMOS!