1

CMOS
Digital Integrated
Circuits
Analysis and Design
Chapter 3
MOS Transistor
2
The Metal Oxide Semiconductor (MOS) structure
The structure consists of three
layer
The metal gate electrode
The insulating oxide (SiO2)
layer
The p-type bulk
semiconductor
The basic properties of the
semiconductor
A p
A
i
n
A
i
N p ,
N
n
econcp tronandhol ibriumelec then equil
n N ncentratio doping co substrate Assume the
n p n ction law: The mass a
~ ~
=
0
2
0
2

n=mobile carrier concentration of electron
P=mobile carrier concentration of hole

3
Energy band diagram of a p-type silicon substrate
) -E (E q q
k f unction ed the wor ce is call o f ree spa l Fermi leve
he ove f rom t ctron to m f or an ele required The energy
n
N
q
kT
ductor, pe semicon For a n-ty
N
n
q
kT
ductor, pe semicon For a p-ty
q
-E E
potential The Fermi
F c s
i
D
Fn
A
i
Fp
i F
F
+ =
=
=
=
int
ln
ln
Electron affinity of silicon is the potential
Difference between the conduction band
Level and the vacuum level and is given by
qx.
4
Energy diagram of the combined MOS system
The equilibrium Fermi levels of the semiconductor (Si) substrate
and the metal gate are at the same potential
The bulk Fermi level is not significantly affected by the bending
The surface Fermi level moves closer to the intrinsic Fermi level
5
Example 1
6
The MOS System under External Bias - accumulation
A negative voltage V
G
is applied to the gate electrode.
The holes in the p-type substrate are attracted to the semiconductor-
oxide surface
The majority carrier concentration > the equilibrium hole concentration
The electron concentration (minority carrier) decreases as the negatively
charged electron are pushed deeper into the substrate
The oxide electric field is directed towards the gate electrode
Causing the energy bands bend up-ward near the surface
7
The MOS System under External Bias depletion
A small positive gate bias V
G
is applied to the gate
electrode
The oxide electric field will be directed towards the substrate
Causing the energy bands to bend downward near the surface
The majority carrier (hole) will be repelled back into the substrate
Leaving negatively charged fixed acceptor ions behind (depletion
region)

F s Si A d A
A
F s Si
d
Si
d A
F s
x
Si
A
s
Si
A
Si
s
A
N q x N q Q
N q
x
x N q
dx
x N q
d
dx
x N q dQ
x d
dx N q dQ
s
F
d
| | c
| | c
c
| |
c
|
c c
|
|
|
= =


=

=

=

= =
=
} }
2
2
2
0
8
F s Si A d A
A
F s Si
d
Si
d A
F s
x
Si
A
s
Si
A
Si
s
A
N q x N q Q
N q
x
x N q
dx
x N q
d
dx
x N q dQ
x d
dx N q dQ
s
F
d
| | c
| | c
c
| |
c
|
c c
|
|
|
= =


=

=

=

= =
=
} }
2
2
2
2
0
Assume that the mobile hole charge in a thin horizontal layer parallel to
the surface is
The change in surface
potential
Required to displace this
charge sheet dQ by a distance
xd away from the surface can
be found by using Poisson
equation

Integrating along the vertical dimension
gives
Thus, the depth of the depletion region
is

And the depletion region charge
density is given by
9
The MOS System under External Bias inversion
A further increase in the positive gate bias
Increasing surface potential the downward bending of the energy bands will increase
The mid-gap energy level E
i
becomes smaller than the Fermi level E
Fp
on the surface
The substrate semiconductor in this region become n-type
The electron density is larger than the majority hole density
Inversion layer, surface inversion
Can be utilized for conducting current between two terminal of the MOS transistor
The surface is said to be inverted
The density of mobile electrons on the surface becomes equal to the density of holes in the bulk
substrate
Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi
potential |
F
Further increase gate voltage electron concentration| but not to an increase of the depletion
depth
A
F Si
dm
N q
x

=
| c 2 2
10
The physical structure of a n-channel
enhancement-type MOSFET
MOS structure
polysilicon gate, thin oxide layer, semiconductor
Source, drain n
+
-region
The current conducting terminals of the device
Conducting channel, channel length L, channel width W
The device structure is completely symmetrical with respect to the drain and source
The simple operation of this device
Controlling the current conduction between the source and the drain, using the electric field
generated by the gate voltage as a control variable

11
Circuit symbols for enhancement-type MOSFET
Enhancement-mode MOSFET
No conducting region at zero gate bias
Depletion-mode MOSFET
A conducting channel already exists at zero gate bias
The abbreviations used for device terminals are
G for the gate, D for the drain, S for the source, and B for the substrate
The small arrow always marks the source terminal
12
Formation of a depletion region
For small gate voltage level
The majority carriers (holes) are repelled back into
the substrate
The surface of the p-type substrate is depleted
Current conduction between S and D is not possible

13
Formation of an inversion layer
As the gate-to-source voltage is further increased
The surface potential reaches -|
Fp
surface inversion will be established conducting
channel between S and D
Allowing current flow, as log as there is a potential difference between S and D
V
GS
<V
T0
(threshold voltage)
Not sufficient to establish an inversion layer
No current between S and D
V
GS
>V
T0
(threshold voltage)
Electrons are attracted to the surface
Contributing to channel current conduction
Further increase gate voltage
Not affect the surface potential and the depletion region depth
14
The threshold voltage
Four physical components of V
T0
The work function difference between
gate and the channel
|
GC
= |
F
(substrate)- |
M
for metal gate
|
GC
= |
F
(substrate)- |
F
(gate) for
polysilicon gate
The gate voltage component to change
the surface potential(to achieve surface
inversion) .To change the surface potential
by -2|
F
The gate voltage component to offset
the depletion region charge
-Q
B
/C
ox

The voltage component to offset the
fixed charge in the gate oxide and in
the silicon-oxide interface(due to
impurities and/or lattice imperfections
at the interface)
-Q
ox
/C
ox

Compared with the p-MOSFET
The substrate Fermi potential |
F
is
negative in NMOS, positive in pMOS
The depletion region charge densities
Q
B0
and Q
B
are negative in nMOS,
positive in pMOS
The substrate bias coefficient is
positive in nMOS, negative in pMOS
The substrate bias voltage V
SB
is
positive in nMOS, negative in pMOS

Threshold voltage adjustment
For n-channel MOS
Implanting p-type impurity V
T

increased
Implanting n-type impurity V
T

decreased
The amount of change in the
threshold voltage as a result of
extra implant
qN
I
/C
ox
where N
i
is the
density of implanted
impurities


ox
ox
ox
SB F Si A B
t
C
V N q Q
c
| c
=
+ = 2 2
( )
t coef f icien ef f ect body bias substrate
C
N q
V V V
C
Q
C
Q
V
ox
Si A
F SB F T T
ox
ox
ox
B
F GC T
) (
2
e wher
effect) body (with 2 2
effect) body (no 2
0
0
0
=

=
+ + =
u =

| |
|
The depletion region charge
Density is given as
15
Example 2
16
Circuit symbols for n-channel depletion-type MOSFETs
Using selective ion implantation into the channel
The threshold voltage for nMOSFET can be made
negative
Having a conducting channel at V
GS
=0
17
Example 3
18
MOSFET operation: linear region
The MOSFET consists
A MOS capacitor, two pn junction adjacent to the channel
The channel is controlled to the MOS gate
The carrier (electron in nMOSFET)
Entering through source, controlling by gate, leaving through drain
To ensure that both p-n junctions are reverse-biased initially
The substrate potential is kept lower than the other three terminal potentials
When 0<V
GS
<V
T0
G-S region depleted, G-D region depleted
No current flow
When V
GS
>V
T0
Conduction channel formed
Capable of carrying the drain current
As V
DS
=0
I
D
=0
As V
DS
>0 and small
I
D
proportional to V
DS
Flowing from S to D through the conducting channel
The channel act as a voltage controlled resistor
The electron velocity much lower than the drift velocity limit
As V
DS
|the inversion layer charge and the channel depth at the drain end start to
decrease
19
MOSFET operation: saturation region
For V
DS
=V
DSAT
The inversion charge at the drain is
reduced to zero
Pinch off point
For V
DS
>V
DSAT
A depleted surface region forms adjacent
to the drain
As further increases V
DS
this depletion
region grows toward the source
The channel-end voltage remains
essentially constant and equal to V
DSAT
The pinch-off (depleted) section
Absorbs most of the excess voltage drop,
V
DS
-V
DSAT

A high-field region forms between the
channel-end and the drain boundary
Accelerating electrons, usually reaching
the drift velocity limit
20
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(1)
Considering linear mode operation
V
S
=V
B
=0, the V
GS
and V
DS
are the external parameters controlling the drain
current I
D
V
GS
> V
T0
(assume constant through the channel) to create a conducting inversion layer
Defining
X-direction: perpendicular to the surface, pointing down into the substrate
Y-direction: parallel to the surface
The y=0 is at the source end of the channel
Channel voltage with respect to the source, V
c
(y)
Assume the electric field E
y
is dominant compared with E
x
This assumption reduced the current flow in the channel to the y-direction only
Let Q
I
(y) be the total mobile electron charge in the surface inversion layer
Q
I
(y)=-C
ox
[V
GS
-Vc(y)-V
T0
]
21
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)(2)
( )
( ) | |
( ) | |
( ) | |
L
W
k where k V V V V
k
I
C where k V V V V
L
W k
I
V V V V
L
W C
I
dV V V V C W L I
dV y Q W dy I
dy
(y) Q W
I
- dR I dV
yis dropalongd Thevoltage

Q
(y) Q W
dy
dR
ce sis l incrementa
The
'
DS DS T GS D
ox n
'
DS DS T GS D
DS DS T GS
ox n
D
V
C T C GS ox n D
V
C I
L
D
I n
D
D C
n
I
I n
n
DS
DS
= =
= =

=
=
=

= =

=
}
} }
2
0
2
0
'
2
0
0
0
0
n
0
2
2
2
2
2
2
) (
mobility electron bulk the of that of half - one about typically is magnitude its and
region, channel the of ion concentrat doping on the dependents mobility surface electron The
) charge layer inversion the of polarity negative the to due is sign (mimus
tan Re
mobility surfacr constant a has layer inversion in the electrons mobile all that Assumeing

22
Example 4
23
MOSFET current-voltage characteristics-gradual
channel approximation (GCA)-saturation region
For V
DS
>V
DSAT
=V
GS
-V
T0




The drain current becomes a function only of V
GS
, beyond the saturation
boundary
( ) ( ) ( ) | |
( )
2
0
2
0 0 0 ) (
2
2
2
T GS
ox n
T GS T GS T GS
ox n
sat D
V V
L
W C
V V V V V V
L
W C
I

24
Channel length modulation
( )
( )
( )
( )
( ) ( )
DS T GS
ox n
D(sat)
DS
DS
DSAT DS
T GS '
ox n
D(sat)
T GS '
ox n
D(sat)
I
'
I
T GS DSAT DS
DS T GS ox I
T GS ox I
V V V
L
W C
I

, V
L
L

V V L
V V
L
W C
L
L
I
V V
L
W C
I
Q w
L-- L
L) (y Q
-V V V , V
V -V V -C L) (y Q
-V V -C ) (y Q
+

=
<<
~


|
|
|
|
.
|

\
|

=
=
=
=
~ =
= =
= =
= =
1
2
1 that Assuming
t coefficien modulation length channel 1 1 use We
2
1
1
2
0 th segment wi channel the of length the is L here
length channel effective The
0
small very become end drain at the charge layer inversion The
saturation of edge at the that Note
is channel the of end drain at the charge layer inversion the and
0
is channel the of end source at the charge layer inversion The
2
0
2
0
2
0
0
0
0
25
Substrate bias effect
The discussion in the previous has been done under the assumption
The substrate potential is equal to the source potential, i.e. V
SB
=0
On the other hand
the source potential of an nMOS transistor can be larger than the substrate
potential, i.e. V
SB
>0



( )
( ) | |
( ) ( )
DS SB T GS
ox n
sat D
DS DS SB T GS
ox n
lin D
F SB F T SB T
V V V V
L
W C
I
V V V V V
L
W C
I
V V V V
+

=
+ + =

| |
1 ) (
2
) ( 2
2
2 2 ) (
2
) (
2
) (
0
26
Current-voltage equation of n-, p-channel MOSFET
( ) | |
( ) ( )
( ) | |
( ) ( )
T GS DS
T GS DS T GS
ox p
sat D
T GS DS
T GS DS DS T GS
ox p
lin D
T GS D
T GS DS
T GS DS T GS
ox n
sat D
T GS DS
T GS DS DS T GS
ox n
lin D
T GS D
-V V V
V V V V V
L
W
C
I
-V V V
V V V V V V
L
W
C
I
V V I
-V V V
V V V V V
L
W C
I
-V V V
V V V V V V
L
W C
I
V V I
s
s +

=
>
s

=
> =
>
> +

=
<
>

=
< =
and
for 1
2
and
for 2
2
for , 0
MOSFET channel - p For
and
for 1
2
and
for 2
2
for , 0
MOSFET channel - n For
2
) (
2
) (
2
) (
2
) (

27
Measurement of parameters- k
n
, V
T0
, and
The V
SB
is set at a constant value
The drain current is measured for different values of V
GS

V
DG
=0
V
DS
>V
GS
-V
T
is always satisfied saturation mode
Neglecting the channel length modulation effect


Obtaining the parameters k
n
, V
T0
, and





( ) ( )
0
2
0 ) (
2
,
2
T GS
n
D T GS
n
sat D
V V
k
I V V
k
I = =
F SB F
T SB T
V
V V V
| |

2 2
) (
0
+

=
28
Measurement of parameters-
The voltage V
GS
is set to V
T0
+1
The voltage V
DS
is chosen sufficiently large (V
DS
>V
GS
-V
T0
) that the transistor
operates in the saturation mode, V
DS1
,

V
DS2

I
D(sat)
-(k
n
/2)(V
GS
-V
T0
)
2
(1+V
DS
)
Since V
GS
=V
T0
+1I
D2
/I
D1
=(1+V
DS2
)/ (1+V
DS1
)
Which can be used to calculate the channel length modulation coefficient
This is in fact equivalent to calculating the slope of the drain current versus drain
voltage curve in the saturation region
The slope is k
n
/2
29
Example 5
30
MOSFET scaling and small-geometry effects
High density chip
The sizes of the transistors are as small as possible
The operational characteristics of MOS transistor will change with the reduction of iys
dimensions
There are two basic types of size-reduction strategies
Full scaling (constant-field scaling)
Constant-voltage scaling
A new generation of manufacturing technology replaces the previous one about
every two or three years
The down-scaling factor S about 1.2 to1.5
The scaling of all dimensions by a factor of S>1 leads to the reduction of the area
occupied by the transistor by a factor of S
2
31
Full scaling (constant-field scaling)
( ) | |
( ) | |
( ) ( )
s resistance abd es capacitanc parasitic various of reduction A
improved down time - charge and up, - charge the of factor a by down scaled is
unchanged virtually remaining area unit per The
scaling full of features attractive most the of one is n dissipatio power the of reduction t significan The
1

n dissipatio power The
1
2 2

current drain mode saturation The
2
1
2
2
2

current drain mode linear The
of factor a by scaled also will the unchanged ratio aspect The
C
area unit per e capacitanc oxide gate The
density doping scaled by the affected tly significan not is mobility surface the Assuming
factor scaling same by the ally, proportion down scaled be must potentials all goal, this achieve To
2 2
2
2
2
2
2
2
'
'
ox

= = =
=

= =
=

=
=

= = =
S C
ity power dens
S
P
V I
S
V I P
S
I
V V
S
k S
V V
k
(sat) I
S
I
V V V V
S
k S

V V V V
k
(lin) I
S k W/L
C S
t
S
t

g
DS D
'
DS
'
D
'
D(sat)
T GS
n '
T
'
GS
'
n '
D
D(lin)
DS DS T GS
n
'
DS
'
DS
'
T
'
GS
'
n '
D
n
ox
ox
ox
ox
ox
n
c c
32
Constant-voltage scaling
( ) | |
( ) | |
( ) ( )
stress - over electrical and breakdown, oxide n, degradatio carrier hot ration, electromig
density power density, current increasing Disadv.
s. constraint level - voltage external the of because
cases practical mamy in scaling full over preferred be may scaling voltage - constant , summarized To
of factor a by incresaed density power The

n dissipatio power The
of factor a by increased density current drain The
2 2

current drain mode saturation The
2
2
2
2

current drain mode linear The
by increased also is parameter uctance transcond The
of factor a by increased is area unit per e capacitanc oxide gate The
relations field - charge the preserve order to in of factor a by increased be must densities doping The
unchanged. remained voltages terminal the and tage supply vol power The
. of factor a by reduced MOSFETare the of dimensions All
3
3
2
2
2
2
2

= = =
=

= =
=

=
=

S
P S V ) I (S V I P
S
(sat) I S V V
k S
V V
k
(sat) I
(lin) I S V V V V
k S

V V V V
k
(lin) I
S
S C
S
S
DS D
'
DS
'
D
'
D T GS
n '
T
'
GS
'
n '
D
D DS DS T GS
n
'
DS
'
DS
'
T
'
GS
'
n '
D
ox
33
Short-channel effects
A MOS transistor is called a short-channel device
If its channel length is on the same order of magnitude as the
depletion region thickness of the S and D junction
The effective channel length L
eff
~ S, D junction depth x
j
Two physical phenomena arise from short-channel effects
The limitations imposed on electron drift characteristics in the
channel
The lateral electric field E
y
increased, v
d
reached saturation velocity


No longer a quadratic function of V
GS
, virtually independent of the
channel length
The carrier velocity in the channel also a function of E
x
Influence the scattering of carriers in the surface



The modification of the threshold voltage due to the shortening
channel length


DSAT ox sat d
L
I sat d sat d sat D
V C v W Q v W dx x n q v W I
eff
= = =
}
) (
0
) ( ) ( ) (
) (
( )
( )
T GS
no
c GS
Si ox
ox
no no
n
V V
y V V
t
Ex
eff
+
=

O
+
=
O +
=
q

c
c

1
) ( 1
1
) (
34
Short-channel effects-modification of V
T
The n
+
drain and source diffusion regions in p-type substrate induce a
significant amount of depletion charge
The long channel VT, overetimates the depletion charge support by the gate
voltage
The bulk depletion region asymmetric trapezoidal shape
A significant portion of the total depletion region charge is due the S and D junction
depletion
( )
( ) ( )
( )
(
(

|
|
.
|

\
|
+ +
|
|
.
|

\
|
+ =
|
|
.
|

\
|
+ ~
|
|
.
|

\
|
+ ~ + + =
= + +
+ + = +
|
|
.
|

\
|
= +

=
|
.
|

\
| +
=
=
1
2
1 1
2
1
2
2 2
1
1
2
1
1
2
1 2
0 2 2
ln
2 2
2 2
2
1
V - V
0
2 2 2
2 2 2
2 2 2
2 0 0 0
0
T0 T0 0
j
dS
j
dD
j
F A Si
ox
T
j
dS
j S
j
dD
j dD j dD dm j j D
dD j dD dm D j D
D j dm dD j
i
A D
DS
A
Si
dD
A
Si
dS
F A Si
D S
B
T
x
x
x
x
L
x
N q
C
V
x
x
x L
x
x
x x x x x x x L
x x x x L x L
L x x x x
n
N N
q
kT
, V
N q

, x
N q

x
N q
L
L L
Q
nnel) (short cha V
35
( )
( ) ( )
( )
(
(

|
|
.
|

\
|
+ +
|
|
.
|

\
|
+ =
|
|
.
|

\
|
+ ~
|
|
.
|

\
|
+ ~ + + =
= + +
+ + = +
|
|
.
|

\
|
= +

=

|
.
|

\
|
+
=
=
1
2
1 1
2
1
2
2 2
1
1
2
1
1
2
1 2
, 0 2 2
ln
2 2
Re , 2 2
2
1
) ( arg , V - V
0
2 2 2
2 2 2
2
2
2
2
0 0 0
0
T0 T0 0
j
dS
j
dD
j
F A Si
ox
T
j
dS
j S
j
dD
j dD j dD dm j j D
D dD j dD dm D j D
D j dm dD j
i
A D
DS
A
Si
dD
A
Si
dS
F A Si
D S
B
T
x
x
x
x
L
x
N q
C
V
x
x
x L
x
x
x x x x x x x L
L SolvingFor x x x x L x L
L x x x x
n
N N
q
kT
, V
N q

, x
N q

x
gionDepth pletion junctionDe N q
L
L L
Q
lregion trapizoida e egionch Depletionr nnel) (short cha V
36
Example 6 (1)
37
Example 6 (2)
38
Example 6 (3)
39
Narrow-channel effect
Channel width W on the same
order of magnitude as the
maximum depletion region
thickness x
dm
The actual threshold voltage of
such device is larger than that
predicted by the conventional
threshold voltage
Fringe depletion region under
field oxide




arcs circular - quarter by modeled region depletion for
2
2 2
1
V
V V channel) narrow (
T0
T0 T0 0
t
k
k
| c
=

= A
A + =
W
x
N q
C
V
dm
F A Si
ox
T
40
Other limitations imposed by small-device geometries
The current flow in the channel are controlled by two dimensional electric field vector
Subthreshold conduction
Drain-induced barrier lowering (DIBL)
A nonzero drain current I
D
for V
GS
<V
T0



Punch-through
The gate voltage loses its control upon the drain current, and the current rises sharply
Gate oxide thickness t
ox
scaled to t
ox
/S, is restricted by processing difficulties
Pinholes, oxide breakdown
Hot-carrier effect
( )
DS GS
r
V B V A
kT
q
kT
q
B
c n
D
e e
L
n Wx qD
ld subthresho I
+
~
|
0
) (
41
MOSFET capacitances
L=L
M
-2L
D
L: the actual channel length
L
M
: the mask length of the
gate
L
D
: the gate-drain, the gate-
source overlap
On the order of 0.1m
42
Oxide related capacitance(1)
The gate electrode overlap
capacitance
C
GD(overlap)
=C
ox
WL
D
C
GS(overlap)
=C
ox
WL
D
With C
ox
=c
ox
/t
ox
Both capacitance do not depend
on the bias condition, they are
voltage-independent
The capacitances result from the
interaction between the gate
voltage and the channel charge
Cut-off mode
C
gs
=C
gd
=0
C
gb
=C
ox
WL
Linear mode
C
gb
=0
C
gs
~C
gd
~(1/2) C
ox
WL
Saturation mode
C
gb
= C
gd
=0
C
gs
~

(2/3) C
ox
WL
43
Oxide related capacitance(2)
The sum of all three voltage-dependent (distributed) gate oxide
capacitances (C
gb
+C
gs
+C
gd
)
A minimum value of 0.66C
ox
WL, in saturation mode
A maximum value of C
ox
WL, in cut off and linear modes
For simple hand calculation
The three capacitances can be considered to be in parallel
A constant worst-case value of C
ox
W(L+2L
D
) can be used for the sum of
MOSFET gate oxide capacitances

44
Junction capacitance(1)
( )
( )
( ) ( )
( )
( )
1 0 2 0
1 2
0
0
0
1
0
2
2
0 0
1
0
1
1
0
2
2
0 0
1 2 1 2
1 2
0
0
0
0
0
0
2 0
0
2
1 1
2
junctions - pn abrupt of case special For the
1 1
1
1
as defined be can e capacitanc signal - large equivalent The
1
2
area unit per e capacitanc junction bias zero The
t coefficien grading is m parameter the ,
1
1
2
e capacitanc junction The
2 charge region depletion The
ln potential in - built The
2
ckness region thi depletion The
2
1
V V
V V
K
K C A C
V V
V V
C A
C
V V
m V V
C A
(V)dV C
V V V V
) (V Q ) (V Q
V
Q
C
N N
N N q
C

V
AC
(V) C
V N N
N N q
A
dV
dQ
C
V
N N
N N
q A x
N N
N N
q A Q
n
N N
q
kT

V
N N
N N
q

x
eq
eq j eq
j
eq
m m
j
V
V
j
j j
eq
D A
D A Si
j
m
j
j
D A
D A Si
j
j
D A
D A
Si d
D A
D A
j
i
D A
D A
D A Si
d

=
=
(

=
(
(

|
|
.
|

\
|

|
|
.
|

\
|



=

= =

|
|
.
|

\
|
+

=
|
|
.
|

\
|

|
|
.
|

\
|
+

= =

=
|
|
.
|

\
|
+

=
|
|
.
|

\
|
=

=

}
| |
|
| |
| |
|
45
Example 7
46
Junction capacitance(2)
( )
eq(sw) jsw eq(sw)
eq(sw)
sw sw
sw
sw eq
j sw j jsw
sw D A(sw)
D A(sw)
Si
sw j
A(sw)
A
K C P C
P
C
V V
V V
K
x C C
N N
N N
q
C
N
N
p
=

=
=

|
|
.
|

\
|
+

=
+
be can ) (perimeter length of sidewall a
for e capacitanc junction signal - large equivalent The
2
factor e equivalenc voltage sidewall The
1
2
as found be can area unit per e capacitanc bias - zero the
, by given is density doping sidewall the Assume
density doping substrate than the
density doping higher a with implant, stop - channel a by surrounded are
region diffusion drain or source MOSFET typical a of sidewalls The
1 0 2 0
1 2
0
) (
0
0
0
| |
|
47
Example 8 (1)
48
Example 8 (2)