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The Maxwell-Boltzmann statistics relates the equilibrium hole concentration to the intrinsic Fermi level: p0 = ni exp((Ei EF)/kT) (2.2)
P substrate
If the applied voltage is increased sufficiently, the bands bend far enough that level Ei at the surface crosses over to the other side of level EF. This is brought about by the tendency of carriers to occupy states with the lowest total energy. In the present condition of inversion the level Ei bends to be closer to level Ec and electrons outnumber holes at the surface.
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Ei at the surface now is below EF by an amount of energy equal to 2 B , where B is the potential difference between the Fermi level EF and the intrinsic Fermi level Ei in the bulk.
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The value of V necessary to reach the onset of strong inversion is called the threshold voltage.
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Threshold voltage
VT = (2d/i ) * ( q s NA B (1 e-2B) )0.5 + 2B The total voltage needed to offset the effect of nonzero work function difference and the presence of the charges is referred to as the flat-band voltage VFB. VFB = ms QT*d/i
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Threshold voltage
VT = (2d/i ) * ( q s NA B (1 e-2B) )0.5 + 2B + VFB
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Drain-induced barrier lowering (DIBL) is the basis for a number of more complex models of the threshold voltage shift. It refers to the decrease in threshold voltage due to the depletion region charges in the potential barrier between the source and the channel at the semiconductor surface.
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A recent model adopt a quasi twodimensional approach to solving the twodimensional Poisson equation. dEx/dx at each point (x, y) can be replaced with the average of its value at (0, y) and at (W, y)
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If the field in the oxide, Eox, is large enough, the voltage drop across the depletion layer suffices to enable tunneling in the drain via a near-surface trap. The minority carriers emitted to the incipient inversion layer are laterally removed to the substrate, completing a path for a gate-induced drain leakage (GIDL) current. In CMOS circuits this leakage current contributes to standby power.
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This advantage of CMOS over NMOS has proven to be important enough that the shortcomings of CMOS are overlooked. The CMOS process is more complex than the NMOS, the CMOS requires use of guard-rings to get around the latch-up problem, and CMOS circuits require more transistors than the equivalent NMOS circuits.
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The threshold voltages place a limit on the minimum supply voltage that can be used without incurring unreasonable delay penalties. If the threshold voltage is too low, the static component of the power due to subthreshold currents becomes significant.
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For simplicity a symmetrical inverter (i.e., N = p and VTn = -Vtp;) and a symmetrical input signal (rise time = fall time) are considered. I = /2(Vin V T)2 for 0 I Imax
Imean = 1/T 0T I(t) dt = 2* 2/T t1t2 /2 (Vin (t) VT)2 dt
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Assuming the rising and falling portions of the input voltage waveform to be linear ramps, Vin(t) = t* VDD/
Imean = 2*2/T(Vt/Vdd) /2 /2(t*VT/ VT)2 dt
Let = (VT/)t - VT
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Imean = - 2/T(Vt/Vdd) /2 d Imean = 1/12*/VDD(VDD VT)3 /T The short-circuit power dissipation of an unloaded inverter is PSC = /12(VDD VT)3 /T
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If the inverter is lightly loaded, causing output rise and fall times that are relatively shorter than the input rise and fall times, the short-circuit dissipation increases to become comparable to dynamic dissipation. To minimize dissipation, an inverter should be designed in such a way so that the input rise and fall times are about equal to the output rise and fall times.
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When V = VDD, E 0->1 = CLVDD2. When energy stored in a capacitor with capacitance CL and voltage VDD across its plates is CL VDD2/2, the rest of the energy, another CL VDD2/2, is converted into heat.
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The overall load capacitance is modeled as the parallel combination of 4 capacitors the gate capacitance Cg, the overlap capacitance Cov, the diffusion capacitance Cdiff, and the interconnect capacitance Cint.
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Finally the fundamental limit based on electromagnetic theory results in the velocity of propagation of a high-speed pulse on an interconnect to be always less than the speed of light in free space, c0: L/ c0 where L is the length of the interconnect and is the interconnect transit time.
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Consider an SOI structure by surrounding the above generic device in a hemispherical shell of SiO2 of radius ri, indicating a twoorder-of-magnitude reduction in thermal conductivity.
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The response time of the global interconnect circuit is = (2.3 Rtr + Rint) Cint where Rtr is the output resistance of the driving transistor and Rint and Cint are the total resistance and capacitance, respectively, of the global interconnect.
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Energy characterization
Transition-sensitive energy models
Single energy tables
Bit independent modules e.g., flipflops
Once constructed, the models can be reused in simulations of other architectures built with the same technology
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Table Compression
Problem
Results in large uncompressed table (e.g., 16-bit adder 232 rows) Excessive simulation (e.g., 232!)
Solution
Clustering Algorithm Reference: Huzefa Mehta, et al. Module Energy Characterization using Clustering, DAC96 For 16-bit adder, to keep 12% average error 1000 simulation points, 97 rows
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000 000
000 001 000 010 000 011 000 100 000 101 000 110 000 111 001 000 001 001
0.00
0.00 0.00 0.00 0.04 0.05 0.04 0.05 0.00 0.00
Compressed
32 rows 000 0xx 000 100 000 101 000 110 000 111 001 0xx 0.00 0.04 0.05 0.04 0.05 0.00
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Simulation based so can be used to support architectural, compiler, OS, and application level experimentation WattWatcher (Sente), DesignPower and PowerCompiler (Synopsys), prototype academic tools (Wattch Princeton, SimplePower PSU)
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