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Sequential logic circuits contain one or more combinational logic blocks along with memory in a feedback loop with the logic
The next state of the machine depends on the present state and the inputs The output depends on the present state of the machine and perhaps also on the inputs
Mealy machine: output depends only on the state of the machine Moore machine: the output depends on both the present state and the inputs
From Chapter 8 in Kang and Leblebici, and portions of Chapter 5 in West and Eshraghian
Bistable circuits have two stable operating points and will remain in either state unless perturbed to the opposite state
Memory cells, latches, flip-flops, and registers
Monostable circuits have only one stable operating point, and even if they are temporarily perturbed to the opposite state, they will return in time to their stable operating point Astable circuits have no stable operating point and oscillate between several states
Ring oscillator
R. W. Knepper SC571, page 5-28
The CMOS SRAM cell at the left will either be in state 0 with V01 at GND and V02 at VDD or in state 1 with V01 at VDD and V02 at GND.
R. W. Knepper SC571, page 5-29
If Reset goes high, M4 is turned on, Q is pulled low, and Q is then pulled high
R=1 Q = 1
If both Set and Reset are low, both M1 and M4 are off, and the latch holds its existing state indefinitely If both Set and Reset go high, both Q and Q are pulled low, giving an indefinite state. Therefore, R=S=1 is not allowed
The gate-level symbol and truth table for the NOR-based SR latch are given at left To estimate Set time, add time to discharge Q + time to charge Q (pessimistic result)
R. W. Knepper SC571, page 5-30
If R goes to 0 (while S = 1), Q goes high, pulling Q low and the latch is Reset
R=0 Q = 1 (if S = 1)
Hold state requires both S and R to be high S = R = 0 if not allowed, as it would result in an indeterminate state
JK Master-Slave Flip-Flop
A Flip-Flop is defined as two latches connected serially and activated with opposite phase clocks
First latch is the Master; Second latch is the Slave Eliminates transparency, i.e. a change occurring in the primary inputs is never reflected directly to the outputs, since opposite phase clocks are used to activate the M and S latches.
The D latch is normally implemented with transmission gate (TG) switches, as shown at the left
The input TG is activated with CLK while the latch feedback loop TG is activated with CLK Input D is accepted when CLK is high When CLK goes low, the input is open-circuited and the latch is set with the prior data D
Timing diagram:
In order to guarantee adequate time to get correct data at the first inverter input before the input switch opens, the data must be valid for a given time (Tsetup) prior to the CLK going low. In order to guarantee adequate time to set the latch with correct data, the data must remain valid for a time (Thold) after the CLK goes low. Violations of Tsetup and Thold can cause metastability problems and chaotic transient behavior.
When CLK is low, the first tri-state goes into its high Z state, while the second tri-state inverter closes the feedback loop, holding the data Q and Q in the latch.
Clock skew problems can be solved onchip by using buffering in clock nets
Inverter buffers to generate neg clk Transmission gate buffers for true clk
D register timing:
Output Q valid at Tq (clock-to-Q) delay after clock edge Data must be valid Ts (setup time) prior to clock edge and Th (hold time) after clock edge
N pull-down trees are the dual of each other P pull-up devices are cross-coupled to latch output Both true and complement outputs are obtained Input pull-down trees may be intermixed, depending on the logic to be implemented
Sample-Set Differential Logic (SSDL): Dynamic CVSL with a Latching Sense Amp
SSDL utilizes a latching sense amplifier to latch output when clock goes high, much like a DRAM sense amplifier When clock is low P1 & P2 precharge while N1 pulls down the N tree logic causing a differential voltage on the internal output nodes When clock goes high, N3-N5 cause the sense amplifier to set and latch
SPICE simulated VTC waveforms with increasing and decreasing input voltage are shown at right. increasing Vin Vth = 3.5 V decreasing Vin Vth = 1.4 V
(b) shows a pipelined system indicative of todays microprocessors and logic systems
Tc = Tq + Td + Ts
Tq is the clock-to-Q output delay of Register A Td is the total worst case delay through the combinational logic Ts is the set-up delay time of Register B
In order to increase frequency in superpipelined and superscalar machines, long combinational logic blocks can be split into smaller combinational blocks and latches used to separate the blocks (rather than full registers)
Improves overall frequency of processor, but adds some delay penalty due to added latches
Example:
Register M1 is set by the clock at Tc1, providing data inputs to the combinational logic and then to register M2 Register M2 is supposed to latch in old data at the same clock edge But, if the delay to Tc2 > Tc1 + Tq1 + logic delay, M2 will incorrectly store the new data rather than the previous data.
R. W. Knepper SC571, page 5-50
(a) no PLL clock skew (b) with PLL on chip (c) using PLL with divide by 4 scheme to achieve 4X freq on-chip (d) use of PLL approach to synchronize data across several chips
R. W. Knepper SC571, page 5-51
(b) VCO frequency is a function of control voltage applied to N pull-downs and current mirror (c) another approach to control frequency by using a variable delay line
MOS capacitance load on each stage is varied by NFET gate voltage
Latch Metastability
Consider the problem of setting a latch when the data is late and/or has a very long rise/fall time and is still changing during the clock transition
if data change is delayed and overlaps clock edge (below), latch may set with new data rather than valid prior data
Data delay = 2.2 ns latch sets correctly at Q=1 Data delay = 2.3 ns latch hangs momentarily at metastable point, but then sets correctly at Q=1 Data delay = 2.4 ns latch hangs momentarily and sets incorrectly at Q=0
Metastable point: non stable point in a latch where Vleft = Vright (neither 0 or 1)
thermal noise will cause latch to move off metastable point and set at a 0 or a 1
How to fix?
speedup the data (register-based synchronizer) delay the clock (introduce an intentional clock delay ---- risky!!)
H tree distribution network often used on chips with area pads (solder bumps)
Master clock is brought on board chip near central part of chip and driven outward with large H interconnection arrangement
Same problem can occur with a glitch in K during CLK high, causing a Reset operation Since the master latch actually sets and latches on the noise glitch, the error is then transmitted to the slave latch during CLK
Result:
Q changes on the positive-going CLK edge NAND #1 pair locks in the valid data at the negative CLK edge The master latch is essentially dynamic, holding the state as charge at the inputs of the two inverters
The latch is responsive to S or R only if CLK is high When CLK is low, the latch retains its present state
Operation:
When clk goes up, output Q is complemented (and master latch is set) When clk goes down, slave latch is set. No change occurs to Q When clear goes high, QM is set to a 1 (Q to a 0)
Operation
Clock = 0:
Master latch is connected to input to receive new D data Slave latch is holding previous data on output and is isolated from input
Clock = 1:
Master latch stops sampling input, latches up the D data at the positive clock edge, and sends it through to the output Q
(b) is a D latch based on an SRAM cell with NFET pull-downs to set latch when Clk goes high
P pull-up devices are wired as a cross-coupled latch designed with a full Vdd signal
Gates of P pull-up transistors are connected below the N cascode transistors for maximum speed
(a) shows a simple inverter (b) shows open drain pull-down complementary outputs
N logic trees connect to d and -d
Examples:
(a) or (b) show simple transmission gate latch concept (c ) tri-state inverter dynamic latch holds data on gate when clk is high (d) and (e) dynamic D register