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Digital circuit Design : An Overview Digital IC technologies and logic circuit families

CMOS Circuit Styles


Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path
no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions)

Dynamic CMOS - relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes
simpler, faster gates increased sensitivity to noise

CMOS Combinational Circuits


Implementation of logic gates and other structures using CMOS technology. Basic element :MOS Transistor 2 types of transistors:
n-channel (nMOS) and p-channel (pMOS) Type depends on the semiconductor materials used to implement the transistor. We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits view pMOS and nMOS transistors as switches.

CMOS transistors as Switches


3 terminals in CMOS transistors: G: Gate D: Drain S: Source

nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF)

pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)

Transistors in Series/Parallel
nMOS in Series
a
X

nMOS in Parallel
Path between points a and b exists if both X and Y are 1 XY

a
X:X

a
X Y X:X

a
Y:Y

Y:Y

Path between points a and b exists if either X or Y are 1 X+Y

pMOS in Series
a
X

pMOS in Parallel
Path between points a and b exists if both X and Y are 0 XY

a
X:X

a
X Y X:X

a
Y:Y

Path between points a and b exists if either X or Y are 0 X+Y

Y:Y

Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)


VDD

PMOS transistors only


In1 In2 InN In1 In2 InN PDN PUN pull-up: make a connection from VDD to F when F(In1,In2,InN) = 1 F(In1,In2,InN) pull-down: make a connection from F to GND when F(In1,In2,InN) = 0 NMOS transistors only

PUN and PDN are dual logic networks

Networks of Switches
In general:
1. 2. 3. 4. nMOS in series is used to implement AND logic pMOS in series is used to implement NOR logic nMOS in parallel is used to implement OR logic pMOS in parallel is used to implement NAND logic
1 is the complement of 3, and vice-versa 2 is the complement of 4, and vice-versa

Observe that:

Threshold Drops
PUN VDD
S

0 VDD CL

PDN
D

VDD 0

VDD
S

CL

Construction of PDN
NMOS devices in series implement a NAND function AB
A B

NMOS devices in parallel implement a NOR function


A+B A B

CMOS Inverter
+V F = X

F = X

Logic symbol GRD Transistor-level schematic

Operation: X=1 nMOS switch conducts (pMOS is open) and draws from GRD F=0 X=0 pMOS switch conducts (nMOST is open) and draws from +V F=1

CMOS NAND
A 0 A B B 0 F 1

0
1 AB

1
0 1

1
1 0

A
B

A B

CMOS NOR
A B A A+B A B 0 B 0 F 1

0
1 1

1
0 1

0
0 0

A B

Complex CMOS Gate


B A C D OUT = !(D + A (B + C)) A D B C