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DMA Versus Polling or Interrupt Driven I/O

Polling and Interrupt driven I/O concentrates on data transfer between the processor and I/O devices. An instruction to transfer (mov datain,R0) only occurs after the processor determines that the I/O device is ready
Either by polling a status flag in the device interface or Waits for the device to send an interrupt request.

Considerable overhead is incurred, because several program instructions must be executed for each data word transferred. Instructions are needed to increment memory address and keeping track of work count. With interrupts, additional overhead associated with saving and restoring the program counter and other state information.

Direct Memory Access (DMA)


To transfer large blocks of data at high speed, an alternative approach is used. Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.

DMA Controller
DMA controller is part of the I/O interface. Performs the functions that would normally be carried out by the processor when access main memory. For each word transferred, it provides the memory address and all the bus signals that control data transfer.

DMA Controller
Although DMAC can transfer data without intervention by the processor, its operation must be under the control of a program executed by the processor. To initiate the transfer of a block of data, the processor sends the starting address, the number of words in the block, and direction of the transfer. Once information is received, the DMAC proceeds to perform the requested operation. When the entire block has been transferred, the controller informs the processor by raising an interrupt signal.

Use of DMA Controllers in a Computer System


Processor Main Memory

Disk/DMA Controller

DMA Controller

Printer

Keyboard

Disk

Disk

Network Interface

How is OS involved
I/O operations are always performed by the OS in response to a request from an application program. OS is also responsible for suspending the execution of one program and starting another.
OS puts the program that requested the transfer in the Blocked state, initiates the DMA operation, starts execution of another program.

When the transfer is complete, the DMA controller informs the processor by sending an interrupt request.
OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.

Registers in a DMA Interface


31 Status and Control IRQ IE Done R / W 30 1 0

Starting Address

Word Count

Cycle Stealing
Requests by DMA devices for using the bus are alwas given higher priority than processor requests. Among different DMA devices, top priority is given to high-speed peripherals (disks, high-speed network interface, graphics display device) Since the processor originates most memory access cycles, it is often stated that DMA steals memory cycles from the processor (cycle stealing). If DMA controller is given exclusive access to the main memory to transfer a block of data without interruption, this is called block or burst mode..

Buffers and Arbitration


Most DMACs have a data storage buffer network interfaces receive data from main memory at bus speed, send data onto network at network speed. Bus Arbitration is needed to resolve conflicts with more than one device (2 DMACs or DMA and processor, etc..) try to use the bus to access main memory.

Bus Arbitration
Bus Master the device that is allowed to initiate bus transfers on the bus at any given time. When the current master relinquishes control, another device can acquire this status. Bus Arbitration the process by which the next device to become bus master is selected and bus mastership is transferred to it.

Arbitration Approaches
Centralized a single arbiter performs the arbitration. Distributed all devices participate in the selection of the next bus master.

Centralized Arbitration
Bus arbiter may be processor or a separate unit connected to the bus.
BBSY BR Processor BG1 DMA Controller 1 BG2 DMA Controller 2

Distributed Arbitration
No central arbiter used Each device on bus is assigned a 4-bit identification number. When one or more devices request the bus, they assert the Start-Arbitration signal and place their 4-bit ID number on ARB[3..0]. The request that has the highest ID number ends up having the highest priority. Advantages offers higher reliability (operation of the bus is not dependent on any one device). SCSI bus is an example of distributed (decentralized) arbitration.