Digital Logic Design

Lecture # 9
University of Tehran
Outline
 MSI Parts as a Decoder
 Multiplexer
 Three State Buffer
 MSI Parts as a Multiplexer
 Realization of Switching Functions
Using Multiplexers
MSI Parts as a Decoder
 Up till now, we saw a modular component
named as a decoder. Let’s now see what
standard modules with that functionality are
available.
 74138: This standard decoder is the most used
in between the MSI decoders. It has active-low
outputs, and one of the enable inputs is also
active-low, while the other two are active-high.
There is no particular reason to why they are
3 enable inputs other than obeying the
7 4 1 3 8
Y 0 N
A Y 1 N
B Y 2 N
C Y 3 N
G 1 Y 4 N
G 2 AY N5 N
G 2 BY N6 N
Y 7 N

1
3 :8 D E C O D E R

standard number of pins these packages have.

MSI Parts as a Decoder
(continued…)
 74154: As in the 74138, this package also
needs activity of both enable pins to work.
7 4 1 5 4
O 0 N
O 1 N
O 2 N
O 3 N
O 4 N
A O 5 N
B O 6 N
C O 7 N
D O 8 N
G 1 O
N 9 N
G 2 O
N 1 0 N
O 1 1 N
O 1 2 N
O 1 3 N
O 1 4 N
O 1 5 N
2 D E C O D E R
MSI Parts as a Decoder
(continued…)
 74139: This decoder is often called a dual 2-to-
4 decoder and is actually just two 2-to-4
decoders in one chip.
7 4 1 3 9
Y 1 0 N
A 1 Y 1 1 N
B 1 Y 1 2 N
A 2 Y 1 3 N
B 2 Y 2 0 N
G 1 N
Y 2 1 N
G 2 N
Y 2 2 N
Y 2 3 N
3 2 :4 D E C O D E R
Multiplexer
 Data is stored as bytes in computer memory.
When discussing data transport, a lot of wiring
would be needed to be able to move 8 bits of a
byte in parallel. Trading cost for performance
we use serial connections to transport one bit
of data at a time. This means we share a
transition line between the source and
destination.
Multiplexer (continued…)
 For instance, in the following diagram, the
transition line works of 1ms between A and A’
and then changes position as the next bit
move on. In this diagram the first box is a
multiplexer and the second a demultiplexer.
The multiplexersMultiplexer
we discussDemultiplexer
have no memory.

A A’
B B’
C C’
D D’
Multiplexer (continued…)
 Let us consider such a module with one output
and four inputs, where one of the four inputs
must be selected for output through 2
selection lines.
MUX
I0 S1 S0 y
I1 0 0 I0
y
I2 0 1 I1
I3 1 0 I2
S1 S0 1 1 I3
Multiplexer (continued…)
 To observe the gate level design of such
structures, let’s consider a dual 4-to-1 MUX
and showS1
its design: S1 S0

S0 } 0/3 1I0
1en
1I1
1en
1I0 1y
1I2
1I1 1y
1I2
1I3
1I3
2I0
2en
2en 2I1
2I0
2I1 2y 2y
2I2
2I2
2I3
2I3
Multiplexer (continued…)
 We need to be able to construct larger
multiplexer modules by cascading smaller
ones. This cascading is done by using the
enable inputs of our smaller modules as shown
in the following
2S S
1 S 0 figure:
S1
S 0 } 0/3

1en
a 1I0
b 1I1 1y
c 1I2
d 1I3
y
2en
e 2I0
f 2I1 2y
g 2I2
h 2I3
Multiplexer (continued…)
y1
 Recall the y
0 structure can be used as
a 1-to-2 decoder which has been used to
choose the particular 4-to-1 MUX to be
enabled in the last example. That is when
s2=0 the upper package is working and when
s2=1 the lower one. We could have used a 2-
to-1 MUX to choose between 1y and 2y and
use s2 as the selector.
Multiplexer (continued…)
 Let’s observe different structures of a 2-to-1
MUX:
s
s
I1
4
6 I1
4 y
6 y
I0
4
6
I0
1 2
Multiplexer (continued…)
 About the second structure as a MUX shown in
the last slide it must be mentioned that it
would have been logically correct use a PMOS
transistor instead of the inverter and NMOS,
but PMOS transistors are much slower than the
same size NMOS transistors, so this structure
is preferred (this structure uses the level
before as its power supply).
Multiplexer (continued…)
 Multiplexers can be used in the design of both
complex circuits and also realization of
primitive gates such as XOR and AND gates.
 XOR gate: If we look at an XOR gate’s functionality a
little differently, we can easily see that when one
input is 0 the other is simply propagated through and
when one is 1 the other is complemented. Using a
multiplexer to realize this, is shown in the following
figure. This realization uses only 6 transistors if we
use the second method used for a 2-to-1 MUX
whereas XOR gates a b yusually consist
a of 8 transistors.
0 0 0 b
0
0 1 1 y
-
1 0 1 b
1
1 1 0
Multiplexer (continued…)
 AND gate: Again we use only 4 transistors instead of
the usual 6 used for an AND gate.

a
a b y
0 0 0 0
0
y 0 1 0
b 1 0 0
1
1 1 1
Three State Buffer
 Another useful and primitive component in
digital circuits is the three state buffer:
c a y
0 0 Z c(control)
0 1 Z ENB y(output)
1 0 0 a(input)
1 1 1

 This three state buffer lets it’s input through to

the output when the control is 1 and give a
high impedance output otherwise.
Three State Buffer
(continued…)
 Different three state buffers that are used, are
listed below:

ENB ENB
buff if 1 not if 1

ENB ENB
buff if 0 not if 0
Three State Buffer
(continued…)
 Let us know use our knowledge of three state
buffers to construct other structures that
realize multiplexers and observe some new
concepts. Thus for aI 4-to-1 MUX,
0 ENB we have:

I1 ENB

I2 ENB

I3 ENB

en y0
y1
0 y2
1 y3
Three State Buffer
(continued…)
 Note: It must be taken to consideration that a
wired OR structure can only be used when we
have three state lines.
 We can do cascading on packages with three
state outputs with the same type of ORing:
a en
I0
b I1
c y
I2
d I3
S1 S0

e en
I0
f I1
g y
I2
h I3 Shows three
S1 S0
state outputs

S2 S 1 S0
MSI Parts as a Multiplexer
 Let us now see some standard multiplexer
packages.
 74153: It’s clear that this package is a dual 4-
A
B
1
1
1
1
1
7

G
C
C
C
C
4

N
0
1
2 1
3 2
1 5

Y
Y
3

to-1 multiplexer.
2 G N
2 C 0
2 C 1
2 C 2
2 C 3
1 M U L T IP L E X E R
MSI Parts as a Multiplexer
(continued…)
 74157: This is a quad 2-to-1 MUX with
common select and enable inputs. Outputs
are not in three state.
2
S
A
B
A
B
A
B
A
B
G
M
7
E
1
1
2
2
3
3
4
4
N
U
4
L

Y
Y
Y
Y

L
1

1
2
3
4

T
5

IP
7

L E X E R
MSI Parts as a Multiplexer
(continued…)
 74251: This is an 8-to-1 MUX that gives us the
complemented form of the output too. The
outputs are three state and the last level of
the MUX can be seen below:
7 4 2 5 1
G N
D 0
D 1
D 2
D 3
D 4 W N
D 5 Y
D 6
D 7
A
B
C
3 M U L T IP L E X E R

EN B
y

... WN
MSI Parts as a Multiplexer
(continued…)
 Note:

ENB
Realization of Switching
Functions Using
Multiplexers
 Multiplexers can also be used to realize more
complex switching functions, for example we
will now realize a full adder using a 74153
multiplexer module.
a b cin co S
a b 0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
cin F . A. cout 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
sum
1 1 0 1 0
1 1 1 1 1
Realization of Switching
Functions Using Multiplexers
(continued…)
ab
00 01 11 10
cin

0 0 1 0 1
0 2 6 4

1 1 0 1 0
1 3 7 5
S
cin cin cin cin

ab
00 01 11 10
cin

0 0 0 1 0
0 2 6 4

1 0 1 1 1
1 3 7 5
co
0 cin 1 cin
Realization of Switching
Functions Using Multiplexers
(continued…)
a 0
b 1 } 0/3

en
cin 0
cin 1 S
2
3

en
0 0
cin 1 co
2
1 3