Beruflich Dokumente
Kultur Dokumente
Introduction
Reading
W&H 3 3 Layout Design Rules W&H 3.3 Layout Design Rules W&H 6.1-6.2.2 Layout parasitics +W&H 3.6 Advanced layout rules
Introduction
In this lecture we look at the effect that fabrication constraints have on the layout we need to 4/22/12 produce For this class we will use a
4/22/12
Layer
Fabrication
Some of these layers are really the combination of layers a designer would like to think about. For example active is really all the diffusion layers merged together. Many of these layers can be derived from other layers. For example the selects 4/22/12 the threshold adjust and
Layer Choice
These tell the tools what to do Allow the tools to handle many different technologies
Dominant
layout editor is
Virtuoso
4/22/12
Stick Diagram
We
Wires on the same layer that 4/22/12 touch ALWAYS connect. There is
Try to keep nMOS devices near nMOS devices and pMOS devices near pMOS devices near pMOS devices.
So
nMOS usually are placed near Gnd, and pMOS near Vdd
4/22/12
Transistor Rules
CMOS
areas where either n- or p-type diffusion is to be placed, or where the gates of transistors are to be placed.
type of diffusion required. n-select 4/22/12 surrounds active regions where n-type
4/22/12
generally
Metal
rules may be complicated by varying spacing dependent on width : as the width increases, the spacing increases. Metal 4/22/12
Via Rules
Vias
are normally of uniform size within layer. They may increase in size toward the top of a metal stack. For instance, large vias required on power busses are constructed from an array uniformly sizes vias. Other Rules
Differing
lengths
SUBM rules are somewhat more conservative than SCMOS rules, DEEP rules are even more conservative.
4/22/12
4/22/12
4/22/12
4/22/12
4/22/12
An Example
Choose global directions for routing layers Position power lines in top/bottom layer of metal
4/22/12
An Example Step 2
Cluster together NMOS with NMOS and PMOS with PMOS Generally keep gate orientation the same 4/22/12
An Example Step 3
An Example Step 4
Connect everything up
4/22/12
4/22/12
We
are creating features smaller than the wavelength of light steps have their own constraints
Processing The
Metal Density
Old rule: minimum metal density For Al, metals were etched away
4/22/12
Antenna Rules
Reactive ion etch charges up metal lines Charge can accumulate and zap a gate oxide If a gate sees a long metal before a diffusion does
4/22/12
Process where the transistors are fabricated on an insulator. Two main insulators are used, SiO2 and sapphire. Advantage : elimination of the capacitance between the source/drain regions and body, leading to higher-speed devices.
4/22/12
Gate Dielectrics
MOS transistors need high gate capacitance to attract charge to the channel very thin SiO2 gate dielectrics. C = .A/d Gate leakage will be unacceptably large in such thin gates. Gates could use thicker dielectrics and hence leak less if a material with higher dielectric constant were available. 4/22/12
Mobility
Increasing the mobility of the semiconductor improves drive current and transistor speed, this has been achieved by using silicon germanium (SiGe) for bipolar transistors. SiGe can be constructed on conventional CMOS processing by adding a few extra implantation steps.
4/22/12
Circuits Elements
Capacitors
The most common capacitor used in CMOS processes today is the MIM (metal-insulator-metal) that is normally placed between metal layers n and n-1 (n is normally the top level metal layer) to minimize the stray capacitance of the bottom plate. Another type of capacitor that is possible in scaled processes is the 4/22/12 fringe (or fractal) capacitor, which is
1-4 fF/um2
4/22/12
Resistor can be built from any layer, with final resistance depending on the resistivity of the layer. Building large resistances in a small area requires layers with high resistivity, particularly polysilicon and diffusion. Another material used for highquality resistors is nichrome need a special4/22/12 steps. proc.
4/22/12
The most common monolithic inductor is the spiral inductor, which is a spiral upper-level metal. The parameters of interest to a designer are its inductance, the Q of the inductor, and self-resonant frequency. High Q low phase-noise osc, narrow filters and low-loss circuits. Q-values 4/22/12 for typical planar inductors
4/22/12
It
Power
can be estimated by simple RC models can be estimated (mostly) from C alone to do either, we need to have a R, C model of gates
Power But
4/22/12
Resistance? Capacitance?
Resistance
Relates current to voltage (V = IR) Measures how easy it is for current to flow (Actually weird relates a force qV/L to a velocity) Relates charge to voltage (Q = CV) Exists between any two conductors
4/22/12
Capacitance
Resistance
Resistance
of a conductor
Resistivity r * Length/Area Designer does not control r, t Generally deal with r/t Called ohm/square (Rsq)
Thats
Transistor Resistance
For
transistors
and L
Designer chooses
W
Wider
transistor
is a surrogate for
1/Ids
4/22/12 R depends on Vdd
4/22/12
4/22/12
Load Capacitance
Cload
Gate capacitance of driven transistors. Diffusion capacitance of source/drain connected to the wire. Wire capacitance 3. Wire capacitance
Today,
a 1u technology is the really cheap technology that students 4/22/12 use and advanced
Real Wires
4/22/12
4/22/12
But
If
Even Better
Let
4/22/12
Homework 1
1.
Consider the design of a CMOS compound OR-OR-AND-INVERT (OA122) gate computing F=(A+B).(C+D).
a.
Sketch a transistor-level schematic Sketch a stick diagram Estimate the area from the stick diagram Layout your gate with a CAD tool using unit-sized transistors (optional) Compare the layout size to the estimated area Consider
b.
c.
d.
e.
2.
Sketch a transistor-level schematic Sketch a stick diagram Estimate the area from the stick diagram Layout your gate with a CAD tool using unit-sized transistors (optional)
b.
c.
d.
e.