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Designing with FPGA and CPLD

PLDs
ROM

PLDs

PLA

FPGA & CPLDs


PLDs are capable to implement sequential circuits, but not capable to implement complete digital system FPGA and CPLDs are:
Flexible Versatile Capable to implement a complete system on a single chip Capable to implement a small microprocessor

FPGA & CPLDs


Basic unit is identical logic cells with programmable interconnections, user can program, hence it is referred as Field devices Different manufacturers: Leading manufacturers: Xilinx Altera

Structure of typical CPLD

CPLD

Interconnctions

CPLDs

FPGA
General Structure

FPGA

XILINX 4000 Series FPGA


Similar to XILINX 3000 Series FPGA, but have more input, output and other features Lay out part of FPGA:

XILINX 4000 Series FPGA

Xilinx 4000 Series FPGA


Array based: 2-dimensional array of logic blocks XC2000 is first generation SRAM based FPGA from Xilinx XC3000 is widely used; recent and popular is XC4000 Features logic blocks (Configurable Logic Blocks) based on LUT (Look-up-tables) LUT is small one bit wide memory, ie LUT with k input has 2^k x 1 bit memory

CLB of XC4000 Series FPGA

The XC4000 CLB contains three separate LUTs Two 4-input LUTS are fed by CLB inputs, and the third LUT can be used in combination with the other two Allows the CLB to implement a wide range of logic functions of up to nine inputs (F1-F4, G1-G4 and H1), two separate functions of four inputs or other possibilities.

CLB of XC4000 Series FPGA

Each CLB also contains two ip-ops with enable input

CLB of XC4000 Series FPGA


It has 4 outputs, 2 from FFS and 2 from combinational logic function generators Two independent S/R input 4000 logic cell also contain dedicated carry logic; each cell has a carry logic for two bits, and the F and G function generators can be used to generate the sum of bits

Carry Logic

Each cell can be programmed as full adder Carry wires between each cells are hardwired, to provide fast propagation of carry M1 programmed MUX selects the direction of carry M2-M4 MUX allows some of F and G function generator inputs come from carries instead of normal function generators This is also used to implement adder/subtracters, incrementer/decrementers, 2s complemeter, counter etc.

Carry Logic

A cell as 2 bit of a full adder

Ai and Bi from F1 and F2, Ai+1 and Bi+1 from G1 and G2, Ci and Ci+1 are connected to carry propagation lines

Connections for 4 bit adder

CLB as RAM

F an G as input F1=G1, F2=G2.. Provide 4 bit address, C2 and C3 form Data input and C1 as write signal

Altera Flex 10k Series CPLD

High density logic along with RAM memory in each device Logic and interconnection is similar to Xilinx FPGAs

Altera 10k Series CPLD


Block diagram

Altera 10K Series CPLD


Each row of logic array contains several LAB (Logic Array Block) and an Embedded Array Block (EAB) Each LAB contains 8 logic elements and a local interconnect EAB contains 2048 bits of RAM EAB and LAB can be connected together through fast row and column interconnect channels Each Input-Output Element (IOE) can be used as input, output or bidirectional pin Each IOE contains a bidirectional buffer and a flip flop to data for input and output

Altera 10k Series CPLD


Single Flex 10k series CPLD contains:
72 to 624 LABs 3 to 12 EABs Up to 406 IOEs Can utilize 10,000 to 100,000 equivalent gates

LAB of Flex 10K Series CPLD

LAB
Contains 8 Logic Element (LE) Local interconnect has 22 or more inputs from row interconnect and 8 input feedbacks from LE outputs Each LE has 4 data input from local interconnect as well as additional control inputs LE outputs are routed to row or column interconnect

LE

Each LE has a function generator that implement any of 4 functions using LUT Cascade chain provide connections to adjacent LEs, hence more than four variables can be implemented

Cascade chain
Cascade chain using AND or in OR configuration is:

EAB

EAB
Inputs from row interconnect goes to local interconnect of EAB and serve as either data input or address Internal memory array can be used as RAM or ROM of size 256x8, 512x4, 1024x2 or 2048x1 Several EAB can be used together to form large memory In synchronize mode all memory inputs and outputs are connected to registers In asynchronous mode registers are bypassed