Introduction to Parallel Processing

Topics Covered
An Overview of Parallel Processing Parallelism in Uniprocessor Systems Organization of Multiprocessor

Flynns Classification System Topologies MIMD System Architectures

An Overview of Parallel Processing

What is parallel processing? Parallel processing is a method to improve computer system performance by executing two or more instructions simultaneously. The goals of parallel processing. One goal is to reduce the wall-clock time or the amount of real time that you need to wait for a problem to be solved. Another goal is to solve bigger problems that might not fit in the limited memory of a single CPU.

An Analogy of Parallelism
The task of ordering a shuffled deck of cards by suit and then by rank can be done faster if the task is carried out by two or more people. By splitting up the decks and performing the instructions simultaneously, then at the end combining the partial solutions you have performed parallel processing.

Another Analogy of Parallelism

Another analogy is having several students grade quizzes simultaneously. Quizzes are distributed to a few students and different problems are graded by each student at the same time. After they are completed, the graded quizzes are then gathered and the scores are recorded.

Parallelism in Uniprocessor Systems

It is possible to achieve parallelism with a

uniprocessor system.

Some examples are the instruction pipeline, arithmetic pipeline, I/O processor.

Note that a system that performs different operations

on the same instruction is not considered parallel. Only if the system processes two different instructions simultaneously can it be considered parallel.

Parallelism in a Uniprocessor System

A reconfigurable arithmetic pipeline is an

example of parallelism in a uniprocessor system.

Each stage of a reconfigurable arithmetic pipeline has a multiplexer at its input. The multiplexer may pass input data, or the data output from other stages, to the stage inputs. The control unit of the CPU sets the select signals of the multiplexer to control the flow of data, thus configuring the pipeline.
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A Reconfigurable Pipeline With Data Flow for the Computation A[i] B[i] * C[i] + D[i]

Data Inputs

0 * LATCH 1 MUX 2 3 S1 S0
0 0

0 | LATCH 1 MUX 2 3 S1 S0
x x

0 + LATCH 1 MUX 2 3 S1 S0
0 1

0 1 MUX 2 3 S1 S0
1 1

To

memory
and registers

Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.

Vector Arithmetic Unit

A vector arithmetic unit contains multiple functional units that perform addition, subtraction, and other functions. The control unit routes input values to the different functional units to allow the CPU to execute multiple instructions simultaneously. For the operations AB+C and DE-F, the CPU would route B and C to an adder and then route E and F to a subtractor for simultaneous execution.
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A Vectored Arithmetic Unit

+ *

Data Inputs

Data Input Connections

Data Input Connections

%
AB+C DE-F
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Organization of Multiprocessor Systems

Flynns Classification

Was proposed by researcher Michael J. Flynn in 1966. It is the most commonly accepted taxonomy of computer organization. In this classification, computers are classified by whether it processes a single instruction at a time or multiple instructions simultaneously, and whether it operates on one or multiple data sets.
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Taxonomy of Computer Architectures

Architecture Categories

SISD

SIMD

MISD

MIMD

4 categories of Flynns classification of multiprocessor systems by their instruction and data streams 13

Single Instruction, Single Data (SISD)

SISD machines executes a single instruction

on individual data values using a single processor. Based on traditional Von Neumann uniprocessor architecture, instructions are executed sequentially or serially, one step after the next. Until most recently, most computers are of SISD type.
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SISD
Simple Diagrammatic Representation

IS

IS

DS

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Single Instruction, Multiple Data (SIMD)

An SIMD machine executes a single instruction on

multiple data values simultaneously using many processors. Since there is only one instruction, each processor does not have to fetch and decode each instruction. Instead, a single control unit does the fetch and decoding for all processors. SIMD architectures include array processors.

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SIMD
Simple Diagrammatic Representation

P
IS

DS

C
P
DS

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Multiple Instruction, Multiple Data (MIMD)

MIMD machines are usually referred to as

multiprocessors or multicomputers. It may execute multiple instructions simultaneously, contrary to SIMD machines. Each processor must include its own control unit that will assign to the processors parts of a task or a separate task. It has two subclasses: Shared memory and distributed memory

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MIMD
IS

IS

DS

M
IS

IS

DS

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Multiple Instruction, Single Data (MISD)

This category does not actually exist. This

category was included in the taxonomy for the sake of completeness.

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MISD

IS

IS

DS

M
IS

IS

DS

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Analogy of Flynns Classifications

An analogy of Flynns classification is the

check-in desk at an airport

SISD: a single desk SIMD: many desks and a supervisor with a megaphone giving instructions that every desk obeys MIMD: many desks working at their own pace, synchronized through a central database

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System Topologies
Topologies

A system may also be classified by its topology. A topology is the pattern of connections between processors. The cost-performance tradeoff determines which topologies to use for a multiprocessor system.

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Topology Classification
A topology is characterized by its diameter,

total bandwidth, and bisection bandwidth

Diameter the maximum distance between two processors in the computer system. Total bandwidth the capacity of a communications link multiplied by the number of such links in the system. Bisection bandwidth represents the maximum data transfer that could occur at the bottleneck in the topology.
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System Topologies
Shared Bus
M M M

Topology

Processors communicate with each other via a single bus that can only handle one data transmissions at a time. In most shared buses, processors directly communicate with their own local memory.

Shared Bus Global memory

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System Topologies
Ring Topology

Uses direct connections between processors instead of a shared bus. Allows communication links to be active simultaneously but data may have to travel through several processors to reach its destination.

P
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System Topologies
Tree Topology

Uses direct connections between processors; each having three connections. There is only one unique path between any pair of processors.

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Systems Topologies
Mesh Topology

In the mesh topology, every processor connects to the processors above and below it, and to its right and left.

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System Topologies
Hypercube Topology Is a multiple mesh topology. Each processor connects to all other processors whose binary values differ by one bit. For example, processor 0(0000) connects to 1(0001) or 2(0010).

P
P

P
P

P
P

P
P

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System Topologies
Completely Connected Topology

Every processor has n-1 connections, one to each of the other processors. There is an increase in complexity as the system grows but this offers maximum communication capabilities.

P P P

P P P

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MIMD System Architectures

Finally, the architecture of a MIMD system,

contrast to its topology, refers to its connections to its system memory. A systems may also be classified by their architectures. Two of these are:

Uniform memory access (UMA) Nonuniform memory access (NUMA)

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Parallel/Vector computers
Parallel computers Execute programs in

MIMD mode Are of two types Shared memory multiprocessors message passing multicomputers The processors in MP communicate through shared variables in common memory

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 Vector computers has multiple vector

pipelines Two families of pipelined vector processor memory to memory register to register

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Development layers
Applications Programming environment Languages supported Communication model Addressing space

Hardware architecture
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System attributes to performance

Clock rate and CPI

Clock has cycle time -- Clock rate f = 1/ Size of program is instruction count (Ic) Cycles per instruction(CPI) time need for executing each instruction

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 Performance factors

CPU time needed to execute the program T = Ic x CPI x Or, T = Ic x (p+m+k) x Where p=no. of processor cycle m = no. of memory references k = ratio between memory cycle and processor cycle

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 System attributes

The performance factors (Ic,p,m,k,) are influenced by

Instruction set architecture Compiler technology CPU implementation and control Cache and memory hierarchy

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 MIPS rate

= Ic/(Tx106) = f/(CPIx106) = (f x Ic)/ (C x 106)

Where C is the total number of clock cycles needed to execute a given program

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 Throughput rate i.e how many programs a

system can execute per unit time Ws = f/(Ic x CPI)

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Uniform memory access (UMA)

The UMA is a type of symmetric

multiprocessor, or SMP, that has two or more processors that perform symmetric functions. UMA gives all CPUs equal (uniform) access to all memory locations in shared memory. They interact with shared memory by some communications mechanism like a simple bus or a complex multistage interconnection network.
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Uniform memory access (UMA) Architecture

Processor 1

Processor 2 Communications mechanism Shared Memory

Processor n
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Nonuniform memory access (NUMA)

NUMA architectures, unlike UMA

architectures do not allow uniform access to all shared memory locations. This architecture still allows all processors to access all shared memory locations but in a nonuniform way, each processor can access its local shared memory more quickly than the other memory modules not next to it.

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Nonuniform memory access (NUMA) Architecture

Processor 1

Processor 2

Processor n

Memory 1

Memory 2

Memory n

Communications mechanism
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The COMA model

Cache only memory architecture (COMA)

is a computer memory organization for use in multiprocessors in which the local memories (typically DRAM) at each node are used as cache. This is in contrast to using the local memories as actual main memory, as in NUMA organizations.

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 The COMA model is a special case of NUMA machine in

which distributed memories are converted into caches There is no memory hierarchy at each processor node All caches form a global address space Remote cache access is assisted by the distributed cache directories Depending on interconnection network used sometimes hierarchical directories may be used to help locate copies of cache blocks Initial data placement is not critical because data will eventually migrate to where it will be used.

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The COMA model

Interconnection network

D C P D C P D

C
P

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Vector Supercomputers
Epitomized by Cray-1, 1976: Scalar Unit + Vector Extensions Load/Store Architecture Vector Registers Vector Instructions Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory

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THE END

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