Digital System Testing

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Why Testing..?

To determine the presence of faults, not the absence of faults, in a given circuit.

No amount of testing can guarantee that a circuit (chip, board or system) is fault free. We carry out testing to increase our confidence in proper working of the circuit.

Verification is an alternative to testing, used to verify the correctness of a design.

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Testing basics

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
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Testing vs. Verification

Verifies correctness of manufactured hardware.

Verifies Verification Testingcorrectness of design. Two-part process:

1. Test generation: software process executed once Performed by during design

simulation, hardware 2. Test application:formal emulation, or electrical tests applied to methods.

hardware

Test application performed on every manufactured device. Responsible for quality of devices.

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Levels of Testing

Testing can be carried out at the level of

Chip Board System It costs 10 times more to test a device as we move to the next higher level in the product manufacturing process.

Cost :: Rule of 10

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Levels of Testing

Other ways to define levels:

Important to develop correct fault models and simulation models.

Transistor Gate RTL (Mux, ALU, Reg, etc.,) Functional/Behavioral

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Costs of Testing

Design For Testability (DFT)

Chip area overhead and yield reduction Performance overhead Test generation and fault simulation Test programming and debugging

Software processes of test

Manufacturing test
Automatic test equipment (ATE) capital 4/27/12 cost

Basic Testing Principle

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Basic Testing Principle

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Defects, Errors, and Faults

Defect: A defect in an electronic system

is the unintended difference between the implemented hardware and its intended design.

Error: A wrong output signal produced

by a defective system is called an error. An error is an effect whose cause is some defect.

the abstracted function level is called a 4/27/12 fault.

Fault: A representation of a defect at

Example

Consider a digital system consisting of two inputs a and b, one output c, and one two-input AND gate. The system is assembled by connecting a wire between the terminal a and the first input of the AND gate. The output of the gate is connected to c. But the connection between b and the gate is incorrectly made b is left unconnected and the second input of the gate is grounded. The functional output of this system, as implemented, is c=0, instead of the correct output c=ab. For this system, we have:

Defect: a short to ground. Fault: signal b stuck at logic 0. Error: a=1,b=1 output c=0; correct output c=1.

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Some Real Defects in Chips

Processing defects

Missing contact windows Parasitic transistors Oxide breakdown ... Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) ... Dielectric breakdown Electromigration

Material defects

Time-dependent failures

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Yield

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing 4/27/12

Yield
Good chips Faulty chips

Defec ts Waf er

Unclustered defects Wafer yield = 12/22 = 0.55

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Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

Fault Modeling

I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing
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A fault model makes analysis possible

Common Fault Models

Stuck-at faults

Single, multiple open and short faults Coupling, pattern sensitive stuck-at, cross-point, bridging

Transistor faults

Memory faults

PLA faults

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Stuck-at Faults

Some lines in the circuit are permanently stuck at logic 0 or logic 1. Two types

Single stuck-at faults Multiple stuck-at faults

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Single Stuck-at Fault

Simpler to handle computationally Reasonably good fault coverage

A test set for detecting single stuck-at faults detects a large percentage of multiple stuck-at faults as well

Three properties define a single stuck-at fault

Only one line is faulty

The faulty line is permanently set to 0 or 1 4/27/12

Single Stuck-at Fault

For a circuit with k lines, the total number of single stuck-at faults possible is 2k. Most widely used fault model in the industry.

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Example 1 (No Fanout)

Test Vector 1 1 0 0
1

True Response
0 (1)

Faulty Response 0 (1)

X Stuckat-1

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Example 2 (Fanout)

XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

Faulty circuit circuit value 1(0)

1 0

a b

c d e

s-a-0

Good j 0(1)value g
1

h i k

z
1

f Test vector for h s-a-0 fault

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Fault sites

Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches).

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Fault Equivalence

Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Two faults of a Boolean circuit are called equivalent iff they transform 4/27/12

Fault collapsing

All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
Set of collapsed faults Collapse Ratio = Set of all faults
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Equivalence Rules
sa0 sa1 sa0 sa1 AND sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NAND sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NOR sa0 sa1 sa0 sa1 FANOUT sa0 sa1 sa0 sa1 NOT sa1 sa0 sa0 sa1 OR sa0 sa1 WIRE sa0 sa1

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Equivalence Example

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Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in blue removed by equivalen ce collapsin g sa0 sa1

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20 Collapse ratio = -----

Fault Dominance

If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing:

If fault F2 dominates F1, then F2 is removed from the fault list.

When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates.
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Fault Dominance

In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. If two faults dominate each other then they are equivalent.

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Dominance Example
F1 s-a-1 All tests of F2

F2 s-a-1

110 101

001 000 100

010 011

s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set 4/27/12

Only test of F1

Dominance Collapsing

An n-input Boolean gate requires n + 1 single stuck-at faults to be modeled. To collapse faults of a gate, all faults from the output can be eliminated retaining one type (s-a-1 for AND and NAND; s-a-0 for OR and NOR) of fault on each input and the other type (s4/27/12 for AND and NAND; s-a-1 for OR a-0

Checkpoints

Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in 4/27/12 that circuit.

Checkpoints

Total fault sites = 16 Checkpoints ( ) = 10 4/27/12

Transistor (Switch) Faults

MOS transistor is considered an ideal switch and two types of faults are modeled:

Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires two vectors.

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Stuck-Open Example
Vector 1: test for A s-a-0 (Initialization vector) pMOS FETs 1 0 0 0 Vector 2 (test for A s-a-1) Two-vector s-op test can be constructed by ordering two s-at tests Stuckopen

VD

A B

C
nMOS FETs 4/27/12

1(Z) Good circuit states

Faulty circuit states

Stuck-Short Example
Test vector for A s-a-0 pMOS FETs 1 0

VD

A B

D
Stuckshort

IDDQ path in faulty circuit

Good circuit state

C
nMOS FETs 4/27/12

0 (X)

Faulty circuit state

Automatic Test-Pattern Generator

ATPG algorithms inject a fault into a circuit, and then use a variety of mechanisms to activate the fault and cause its effect to propagate through the hardware and manifest itself at a circuit output.

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Random Pattern Generation

Start Set input probabilities

Generate a random vector Simulate Faults Change Probabilities

Inadequate
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Check Coverage Adequate Stop

Random Pattern Generation

Use to get tests for 60-80% of faults, then switch to ATPG(Automatic Test Pattern Generation) for rest.
Fault Coverage 100 %

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30 0

No. of patterns

Functional vs Structural ATPG

Functional ATPG programs generate a complete set of test-patterns to completely exercise the circuit function. Structural test only exercises the minimal set of stuck-at faults on each line of the circuit, after discarding equivalent faults.
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Functional vs Structural ATPG

Example 64 bit adder

Functional Block

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Functional ATPG

Generate complete set of tests for circuit input-output combinations.

129 inputs, 65 outputs

2129 = 680,564,733,841,876,926,926,749,214,863,536,422,912

input patterns required.

Fastest automatic test equipment (ATE), operating at 1GHZ would take 2.1580566142x1022 years to apply all these patterns.

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Structural ATPG
Sum Circuit

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Structural ATPG
Carry Circuit

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Structural ATPG

In the adder

No redundant adder hardware, 64 bit slices. Each with 27 faults At most 64x27 = 1728 faults (tests) Takes 0.000001728 s on 1GHZ ATE.

In practice
Designer gives small set of functional tests. 4/27/12

Design For Testability (DFT)

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Definition

Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits:

Ad-hoc methods Structured methods:

Scan Partial Scan Built-in self-test (BIST) Boundary scan

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method for mixed-signal circuits:

Ad-hoc methods
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Ad-Hoc DFT Methods

Good design practices learnt through experience are used as guidelines:

Do-s and Donts

Avoid asynchronous (unclocked) feedback. Avoid delay dependant logic. Avoid self resetting logic. Avoid gated clocks. Avoid redundant gates. Avoid large fanin gates. Make flip-flops initializable. Separate digital and analog circuits.

4/27/12 Provide test control for difficult-to-control signals.

Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods:

Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.

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Structured methods
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1.Scan Design

Objectives

Simple read/write access to all subset of storage elements in a design. Direct control of storage elements to an arbitrary value (0 or 1) Direct observation of the state of storage elements and hence the internal state of the circuit.

Enhanced controlability and observability 4/27/12

Scan Design

Circuit designed using pre-specified design rules. Test structure added to the verified design

Add one(or more) test control(TC) primary input. Replace flip-flops by scan flip-flops and connect to form one or more shift registers in the test mode. input/output of each scan shift

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Scan Design

Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

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Scan Design Rules

Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops.

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Correcting a Rule Violation a Rule Violation Correcting

All clocks must be controlled from PIs.
Com b. D logic 1 D 2 Q Com b. logic

C K

F F Com b. logic D D 1 C 2 K

F F

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Q Com b. logic

Scan Flip-Flop (SFF)

D T C S D C K C K T 4/27/12 C Master latch
Logic overhead

Slave latch

Q Q

MU X D flipflop Master open Slave open Scan mode, SD selected t t

Normal mode, D selected

Adding Scan Structure

PI Combinational logic SFF SFF SFF PO SCANOUT

TC or TCK SCANIN
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Not shown: CK or MCK/SCK feed

Combinational Test Vectors

P I I1 SCAN IN TC Presen S t state 1

I2

Combination al logic

O 1

O 2

P O SCANO UT Nex t state

S 2

N 1

N 2

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Testing Scan Register

Scan register must be tested prior to application of scan test sequences. A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.
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Multiple Scan Registers

Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCAN Combination IN al SF logic F SF SF F F T C C 4/27/12 K
M U X

Scan Overheads

IO pins: One pin necessary. Area overhead:

Gate overhead = [4 nsff/(ng+10nff)] x 100%,

where ng = comb. gates; nff = flip-flops; Example ng = 100k gates, nff = 2k flipflops, overhead = 6.7%.

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More accurate estimate must consider scan wiring and layout area.

Hierarchical Scan

Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages:

Automatic scan insertion in netlist Circuit hierarchy preserved helps in debugging and design changes

Scanou ScaniDisadvantage: Non-optimum chip layout. SFF SFF t n SFF 4 1 Scani 1 n SFF SFF SFF 3 2 4 Hierarchical Flat 4/27/12 netlist layout

SFF 3 SFF 2

Scanou t

Scan Design - Summary

Scan is the most popular DFT technique:

Rule-based design Automated DFT hardware insertion Combinational ATPG Design automation High fault coverage; helpful in diagnosis Hierarchical scan-testable modules are easily combined into large scan-testable systems

Advantages:
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Scan Design - Summary

Disadvantages:

Additional pin requirement. Test hardware slows down the clock Large test data volume and long test time Basically a slow speed (DC) test

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2.Partial-Scan Definition

A subset of flip-flops is scanned. Objectives:

Minimize area overhead and scan sequence length, yet achieve required fault coverage Exclude selected flip-flops from scan:

Improve performance Allow limited scan design rule violations

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Allow automation:

In scan flip-flop selection

Partial-Scan Architecture
P I Combination al circuit F F F F SF F SF F P O

CK 1 CK 2 T C
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SCANO UT

Partial-Scan -Summary

Partial-scan is a generalized scan method; scan can vary from 0 to 100%. Partial-scan has lower overheads (area and delay) and reduced test length. Partial-scan allows limited violations

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3.Built-In Self-Test (BIST)

Useful for field test and diagnosis (less expensive than a local automatic test equipment) Software tests for field test and diagnosis:

Low hardware fault coverage Low diagnostic resolution Slow to operate Lower system test effort

Hardware BIST benefits:

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Test Problems Alleviated by BIST

Increasing chip logic-to-pin ratio harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for 1 GHz clocking chips 4/27/12

BIST Costs

Chip area overhead for:

Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware

Pin overhead -- At least 1 pin needed to activate BIST operation Performance overhead extra path delays due to BIST

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BIST Architecture

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BILBO Built-in Logic Block Observer

Programmable hardware block.

Can work as both a Test Pattern Generator(TPG) and a Response Compactor(RC).

Four modes of operation:

1. Flip-flop 2. LFSR pattern generator 3. LFSR response compacter 4. Scan chain for flip-flops
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LFSR

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4.Boundary Scan

IEEE 1149.1 JTAG Boundary Scan Standard

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System Test Logic

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Elementary Boundary Scan Cell

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Serial Board / MCM Scan

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Parallel Board / MCM Scan

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Tap Controller Boundary Scan Instructions

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TESTING -PORTIONS

ROTH-339 to 354 ,361 to 365 P 457 to461 p477 ,481 to 483, P 1-8 ,p93 to 106 P 343 to 369

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Thank You
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All the Best

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