Digital Electronics

Electronics Technology Landon Johnson

Multiplexers Demultiplexers

Mux/Demux Competencies
47. Given 2 logic symbols, the student will identify the multiplexor and demultiplexor with 100% accuracy. 48. Given four different input combinations to an 8 to 1 multiplexor, the student will state the output logic levels for each input combination with 100% accuracy. 49. Given four different input combinations to a 1 to 8 demultiplexor, the student will state the output logic levels for each input combination with 100% accuracy. 50. Given a Boolean equation the student will draw a multiplexor circuit that will implement this function with 100% accuracy. 51. Given a Boolean equation the student will draw a demultiplexor circuit that will implement this function with 100% accuracy.

Mux/Demux Vocabulary
MULTIPLEXER (aka DATA SELECTOR)- circuit that can select one of a number of inputs and pass the logic level of that input to the output.
DEMULTIPLEXER (aka DATA DISTRIBUTOR)- circuit that depending on the status of its select inputs will channel its data input to one of several outputs. SELECT INPUTS (aka ADDRESS LINES)- used by the mux to determine which data inputs will be switched to the output.

if 2 N input lines N select lines

BASIC TWO-INPUT MULTIPLEXER

I1 DATA INPUTS I0

Z I 0 S I1 S

S SELECT INPUT

S 0 1

OUTPUT Z=I0 Z=I1

FOUR-INPUT MULTIPLEXER
I0

I1

I2

I3

S1 S0

S1 0 0 1 1

S0 0 1 0 1

OUTPUT Z=I0 Z=I1 Z=I2 Z=I3

8-to-1 ENCODER

MULTIPLEXER LOGIC DIAGRAM

Takes one of many inputs and funnels it to an output Z. Take the selector lines convert to a decimal number and this is the input funneled to the output. Strobe is active low enable
D A T A I N P U T S I0 I1 I2 I3 I4 I5 I6 I7 E S2 S1 S0 74151 M UX Z _ Z

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

E 0 0 0 0 0 0 0 0

Z I0 I1 I2 I3 I4 I5 I6 I7

SELECT LINES

MULTIPLEXER APPLICATIONS
DATA ROUTING
PARALLEL-TO-SERIAL CONVERSION OPERATION SEQUENCING IMPLEMENT LOGIC FUNCTION OF A TRUTH TABLE

LOGIC FUNCTION GENERATION

+5

I0 I1 I2 I3 I4 I5 I6 I7 E S2 S1 S0 74151 M UX

Z ABC ABC ABC

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 1 1 0 0 0 0 1

TEST
FILL IN THE TABLE
1 0 1 0 1 0 1 0 I0 I1 I2 I3 I4 I5 I6 I7 S2 A S1 B S0 C M UX

f(ABC)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

TEST
FILL IN THE TABLE
1 0 1 0 1 0 1 0 I0 I1 I2 I3 I4 I5 I6 I7 S2 A S1 B S0 C M UX

f(ABC)

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 1 0 1 0

TEST
FILL IN THE TABLE
L M N O I0 I1 I2 I3 S1 B S0 C I0 I1 S0 A S0 C Y

P Q

I0 I1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

TEST
FILL IN THE TABLE
L M N O I0 I1 I2 I3 S1 B S0 C I0 I1 S0 A S0 C Y

P Q

I0 I1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y L M N O P Q P Q

TEST
WRITE A BOOLEAN EXPRESSION FOR THE CIRCUIT

1 0 1 1

I0 I1 I2 I3 S1 A S0 B f(AB)

AB AB AB

DEMULTIPLEXER 1-of-8 DECODER

DEMULTIPLEXER LOGIC DIAGRAM

Logic circuit that depending on the status of its select inputs will funnel its data input to one of several data outputs. Separate enable inputs (useful for cascading decoders) into AND gate which must be high to enable the decoder outputs.
O0

E3
E2 E1

O1 E
74138 DEMUX 1-OF-8 DECODER

O2 O3 O4 O5
O6 O7

E1 E 2
0 1 X X 0 X 1 X

E3
1 X X 0

OUTPUTS
RESPOND TO INPUT CODE A2A1A0 DISABLED ALL HIGH DISABLED ALL HIGH DISABLED ALL HIGH

A2

A1

A0

SELECT LINES

LOGIC FUNCTION GENERATION

74138

O0

O1

+5 E3
E2

O2 O3 O4 O5
O6 O7

f(ABC)

E1

A2 C

A1 B

A0 A

A 0 0 1 1

B 0 1 0 1

X 1 1 1 0

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

NAND- any low in gives a high out

LAB 35. A SECURITY MONITORING SYSTEM

TEST
NAME THE CIRCUIT
O0

O1 O2 O3

E3
E2 E1

O4 O5
O6 O7

A2

A1

A0

TEST
NAME THE CIRCUIT
I0 I1 I2 I3 I4 I5 I6 I7 E S2 S1 S0

TEST
STATE THE BOOLEAN EXPRESSION
+5

I0 I1 I2 I3 I4 I5 I6 I7 E S2 A S1 B S0 C M UX 74151

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

CBA CBA CBA

TEST
STATE THE BOOLEAN EXPRESSION
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F

74138

O0

O1

+5 E3
E2

O2 O3 O4 O5
O6 O7

E1

A2 A

A1 B

A0 C

CBA CBA CBA

f(ABC)