MENTOR: SANJEEV

POORVA ANAND GROUP-11(ECE)

OUTLINE

MEMORY RAM AND ROM DRAM SDRAM DDR2 SDRAM

MEMORY

MEMORY

Storage Unit Programs Data

on permanent or temporary basis

TYPES OF MEMORY
RAM

ROM

Random Access Memory Volatile Stored data to be accessed in any order TYPES SRAM DRAM

Read Only Memory Non-Volatile Cannot be modified TYPES PROM EPROM EEPROM

DIFFERENCE BETWEEN SRAM &DRAM

STATIC RAM

DYNAMIC RAM

Bi-stable Latch Very Fast Low Density No Refresh

Capacitor Fast High Density Refresh Required

DYNAMIC RAM

DYNAMIC RAM
Use charge storage on capacitor DYNAMIC because stored charge leaks away WRITE: Set BL to 0/Vcc Enable WL READ: Set BL to Vcc/2 Enable WL

WORKING OF DRAM

EXECUTE INSTRUCTION

BUS TRANSMISSION

ROW ACCESS

COLUMN ACCESS

DATA TRANSFER TO MEMORY CONTROLLER

REFRESH MODE OF DRAM

After every 50ms to maintain data integrity Row address provided by refresh counter Loss of bandwidth WAYS TO PERFORM RAS only CAS before RAS Hidden

TYPES OF DRAM

SYNCHRONOUS DRAM

FEATURES
Synchronous operation Pipelining Controls with commands Multiple bank configuration of internal memory circuits Adoption of control by mode registers Selectable burst length Selectable CAS# latency

GENERATIONS

SINGLE DATA RATE SDRAM- R/W 1 word

per clock cycle

DOUBLE DATA1 RATE SDRAM- R/W 2

words per clock cycle

DOUBLE DATA2 RATE SDRAM- doubles

R/W unit to 4 consecutive words

DOUBLE DATA3 RATE SDRAM- doubles

R/W unit to 8 consecutive words

DOUBLE DATA4 RATE SDRAM

SDRAM OPERATION
OPENING a row by ACTIVE command Trcd (MIN) determine the earliest clock edge after ACTIVE on which R/W command can be entered.

SDRAM OPERATION
READ-starting column and bank address provided with READ command

SDRAM OPERATION
WRITE-starting column & bank address provided with WRITE command.

DOUBLE DATA RATE2 SDRAM

FEATURES

Double pumping data bus DUAL channel architecture Allows higher bus speed Requires low power by running internal clock at half the speed of clock speed of data bus Transfer rate=(memory clock rate) X 2 (for bus clock multiplier) 2 (for dual rate) 64 (number of bits transferred) / 8 (number of bits/byte)

4BIT - PREFETCH
Higher speed R/W 4 times data as an external bus from/to memory cell array for every clock cycle.

ON DIE TERMINATION

DRAM controller set termination register for every signal on and off Advantages Reduction of part costs System integrity Easier system design

OFF-CHIP DRIVER CALIBERATION

I/O driver resistance is set to adjust voltage to equalize pull up/down resistance. Improves signal integrity and quality , absorbs process variations

POSTED CAS & ADDITIVE LATENCY

After RAS ,CAS signal can be input to next clock CAS command held by DRAM side & executed after additive latency(0,1,2,3&4) Improved bandwidth , command & data bus efficiency Easier controller design

SUMMARY

Memory and its types-RAM & ROM DRAM-Denser memory Synchronous DRAM- have synchronous operation - pipelining DDR2 DRAM- greater bandwidth & speed - lesser noise & power consumption - higher density and signal integrity

REFERENCES
1. Breth Keeth , Semiconductor Memories , The International Arab Journal of Information Technology, April 2006, Vol 3, No. 2. 2. David Tawei Wang , Modern DRAM Memory Systems: Performance Analysis and a High Performance, PowerConstrained DRAM-Scheduling Algorithm. Masters Thesis in Computing Science, Umea University, Sweden Department of Computing Science June 15, 2006. 3. Dean Kent , RAM Guide: SLDRAM, Toms Hardware, July 2007 4. Ramesh Bangia, Computer Hardware and Applications , Firewall Media, May 2004 5. Razak Mohammed Ali , "DDR2 SDRAM interfaces nextgensystems" (PDF), Journal of Engineering Science and Technology Review 3 (1) (2010) 162-167. 6. Yueh-Min Ray,Advances in multimedia information processing, Journal of Electrical Engineering Science Cheng Kung University, Taiwan, June 1999, Vol 4