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The following discussion will concentrate on the wellestablished CMOS fabrication technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors be built on the same chip substrate. To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created in a ptype substrate. In the simple n-well CMOS fabrication technology, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate.
D p+
D
n+
G S n+ p-well
n-MOSFET
+VDD p+
n+
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The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown.
The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate. Then, a thick oxide is grown in the regions surrounding the nMOS and pMOS active regions. The thin gate oxide is subsequently grown on the surface through thermal oxidation. These steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop implants).
Metallization
S
p+
D p+
D n+
G S n+ p-well +VDD p+
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PhotoResist
PhotoResist normally comes in powder form, which is insensitive to light. It is reconstituted into liquid form by adding a solvent, typically alcohol. The wafer is mounted on a turntable, spinning slowly, and the photoresist is discharged into its center. Centrifugal force spreads the resist outward across the wafer. The thickness that remains on the wafer is a function of the rate of wafer spin and the viscosity of the photoresist. The thickness is monitored by light diffraction, which is used to adjust the spin rate to reach the correct PR thickness.
Phase Interference gives Photoresist Thickness
After the PR is applied, the wafer is heated (~160C) to evaporate the solvent, leaving a smooth solid coating.
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The wafer is protected from light, and is put into the photo-lithography tool. Light is focussed on the wafer, delineating the IC pattern. The wafer is removed and immersed in a Developer Solution. If the PR is positive resist, then those areas which received light will dissolve away. Negative resist reacts the opposite way, with those areas which were NOT exposed to light being dissolved. This step will leave holes in the resist layer. The wafer is then heated to harden the patterned resist so that it will withstand immersion into acids. A typical hardening bake is ~300C. The wafer then re-enters the processing line, for either etching or deposition in the patterned holes. In rare cases, the photoresist is not adequate as a mask itself, and the patterns are processed to make a more robust mask, e.g. of thick SiO2 (for very high energy implants) or Si3N4 for solvent etches which also attack PR.
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PhotoResist
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PhotoResist
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The process starts with the oxidation of the silicon substrate (a), in which a relatively thick silicon dioxide layer (5000A), also called field oxide, is created on the surface (b). Then, the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created (c). Following this step, the surface is covered with a thin, high-quality oxide layer (25A), which will eventually form the gate oxide of the MOS transistor (d). On top of the thin oxide, a layer of polysilicon (polycrystalline silicon, 3000A) is deposited (e). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively high resistivity. The resistivity of polysilicon can be reduced, however, by doping it with impurity atoms. After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (f). The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (g). The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (in this case with donor atoms to produce n-type doping).
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We have covered (1) the basic process steps for pattern transfer through lithography, and (2) gone through the fabrication procedure of a single n-type MOS transistor. Now we consider the fabrication sequence of n-well CMOS integrated circuits. Shown are both the top view of the lithographic masks and a crosssectional view of the relevant areas. The n-well CMOS process starts with a moderately doped (impurity concentration ~1016/cm3) p-type silicon substrate. Then, an initial thick field oxide layer (5000A) is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Once the n-well is created, the active areas of the nMOS and pMOS transistors can be defined. The next figures show the significant milestones that occur during the fabrication process of a CMOS inverter. Following the creation of the n-well region, a thick field oxide is grown around the transistor active regions, and a thin gate oxide (25A) is grown on top of the active regions.
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The polysilicon layer (3000A) is deposited using chemical vapor deposition (CVD) and patterned by dry plasma etching. The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as selfaligned masks for the source and drain implantations that follow this step
CMOS n-Well
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Silicon substrate
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Using a set of two masks, the n+ and p+ Source and Drain regions are implanted into the substrate and into the n- well, respectively. The ohmic contacts to the substrate and to the n-well are implanted in this process step. (If a doped silicon region is partially doped to >1018/cm3, then metal contacts to that volume are almost always ohmic (no Shottkey Barrier effect). The possibility of a Shottkey Barrier effect is always possible, and care must be made of the selection of doping and metal contacts.)
CMOS n-Well
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An insulating silicon dioxide layer is deposited over the entire wafer using CVD (5000A). This is for passivation, the protection of all the active components from contamination. The contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.
(CVD = Chemical Vapor Deposition, where reactive gases collide above the wafer, and chemical reaction products then fall onto the wafer creating a new layer.)
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CMOS n-Well
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Metal (aluminum, >5000A) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability. Since the metal connects two separate devices, it is called Local Interconnect. The connection of adjacent devices is often called LI-1, as being the lowest level of interconnection.
CMOS n-Well
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Interconnection Materials
Polysilicon interconnects are used to connect Gates and other short-distance connections which have minimal currents. Polysilicon is a very stable material that rarely interacts with nearby materials. Metal interconnects have 3-5x the speed of polysilicon (electron mobility is higher) and less resistance. However, metals may react with nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4 or TiN) to prevent unwanted reactions, or partial erosion in subsequent etching procedures. This is expensive. In Upper Metallurgy (not local interconnects) metal is always used because processing is simple: only Metal + SiO2.
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The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections. The final step is to deposit a full SiO2 passivation layer (5000A), for protection, over the chip, except for wire-bonding pad areas. If the wafer will be stored for some months, a final thin blanket layer of Si3N4 may be applied to prevent penetration by water vapor. Completed FEOL wafers are sometimes stored for more than a year before processing in a BEOL factory.
CMOS n-Well
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The patterning process by the use of a succession of masks and process steps is conceptually summarized below. It is seen that a series of
CMOS n-Well
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This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. In the conventional n-well CMOS process, the doping of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics (possible latchup). The twin-tub process, below, avoids this problem.
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For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one well. The substrate should be doped to about 1016/cm3, with a resistivity of about 1 -cm. This allows simpler construction, with good Ground Potential distribution, but the devices are not optimal and there is a chance of latch-up if the voltages are pushed hard. For high-performance chips, one uses a low doped substrate, 1015/cm3, 10 -cm, and then constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity.
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References
CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici W. Maly, Atlas of IC Technologies, Menlo Park, CA: Benjamin/Cummings, 1987. A. S. Grove, Physics and Technology of Semiconductor Devices, New York, NY: John Wiley & Sons, Inc., 1967. G. E. Anner, Planar Processing Primer, New York, NY: Van Nostrand Rheinhold, 1990. T. E. Dillinger, VLSI Engineering, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988. S.M. Sze, VLSI Technology, New York, NY: McGrawHill, 1983.
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