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Overview
Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com
Moore’s Law
• Propounded by Gordon Moore in the 1960’s
• Predicts that the complexity of ICs increases
exponentially
• Caused by a steady decrease in minimum
feature size
• Produces increases in speed
• Moore’s Law is the reason microelectronics
has dramatically changed our lives in the last
three decades
Microelectronics
Technology
Micro Electronics
Silicon GaAs
Fast
MOS Bipolar
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1959
1960
1961
1962
1972
1973
1974
1975
Evolution in Complexity
Transistor Counts
1 Billion
K Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Courtesy, Intel
Moore’s law in Microprocessors
1000
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Courtesy, Intel
Die Size Growth
100
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
Courtesy, Intel
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years
Courtesy, Intel
Minimum Feature Size Trend
N-MOSFET
layout
VLSI Tech: CMOS
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel
n substrate S substrate connected
to VDD
Key feature: p transistor
transistor length L 2002: L=130nm
Polysilicon Gate
SiO2 2003: L=90nm
Insulator L D D
2005: L=65nm
W
Source Drain
G SB G
n+ n+
channel
p substrate S S
substrate connected
n transistor to GND
FABRICATION
PROCESS
Fabrication of MOS Transistor
The MOS fabrication process consists of
• Wafer preparation
• Several steps of photolithography
• Etching
• Oxidation
• Diffusion
• Ion Implantation
• Deposition
Diffusion
Ion Implantation
Deposition
Materials
• Single crystal silicon – SCS
– Anisotropic crystal
– Semiconductor, great heat conductor
• Polycrystalline silicon – polysilicon
– Mostly isotropic material
– Semiconductor
• Silicon dioxide – SiO2
– Excellent thermal and electrical insulator
– Thermal oxide, LTO, PSG: different names for different
deposition conditions and methods
• Silicon nitride – Si3N4
– Excellent electrical insulator
• Aluminum – Al
– Metal – excellent thermal and electrical conductor
Silicon properties
• Semiconductor
– Electrical conductivity varies over ~8 orders of
magnitude depending on impurity concentration (from
ppb to ~1%)
– N-type and P-type dopants both give linear
conduction, but from fundamentally different
mechanisms
– N-type touching P-type forms a diode
• Cubic crystal
– Diamond lattice
– Anisotropic mechanical properties
Periodic Table
Step 1: Obtaining the Sand
• The sand used to grow the wafers has to
be a very clean and good form of silicon.
• For this reason not just any sand scraped
off the beach will do.
• Most of the sand used for these processes
is shipped from the beaches of Australia.
FABRICATING SILICON
• Quartz, or Silica, Consists of Silicon Dioxide
• Sand Contains Many Tiny Grains of Quartz
• Silicon Can be Artificially Produced by
Combining Silica and Carbon in Electric
Furnice
• Gives Polycrystalline Silicon (multitude of
crystals)
• Practical Integrated Circuits Can Only be
Fabricated from Single-Crystal Material
Step 2: Preparing the Molten
Silicon Bath
mask
exposed
Photo resist layer
Si3N4
SiO2
WAFER
Removal
Development
Coverage
Exposed
Masking
of +
the
Etching
Wafer with
of
Photo
+
photo
of the
photo
exposure
the
Oxide photo
resist
resist
lacquer
nitride
(or resist
layer
Nitride)
Semiconductor Manufacturing Process
CMOS VLSI
CMOS Technology
• N-well process
• P-well process
• Twin-tub process
• Silicon on insulator.
P-Wells and N-Wells
IN
P substrate N substrate
contact
G OUT G contact
D S
n+ n+ p+ p+
p+ n+
P-well N-well
n+ n+ p+ p+
p
p-well
n-
P-well CMOS Process
•P-impurity level at the
bottom boundary of the p-
well is exactly equal to the n-
substrate doping
n-substrate
n+
concentration.
p-well
•The impurity concentration
n+ where the n-channel
transistors are formed at p-
z well surface is about 10 times
larger than the p-well bottom.
•The performance of the
nMOS transistor affected by
WELL
p-dope
lower mobility of holes,
relatively large source/drain
z capacitance and a large body-
SUBSTRATE
n-dope effect.
•Development and application
of pure p-well CMOS process
is stagnated totally.
N-Well CMOS Process
• Typical fabrication processes for n-well are similar
to that of p-well process except that n-well is
implanted rather than p-well.
• N–well CMOS circuits are superior to P-well
because of lower substrate bias effects on
transistor threshold voltage & inherently low
parasitic capacitance associated with source &
drain regions and also lower mobility of holes ( µ p ≈
µ n/3).
nMOST pMOST
n+ n+ p+ p+
n
n-well
p-
Twin-tub CMOS process
• One type of transistor is always affected by a low
performance due to the necessarily high dope of the
well in both the previous methods.
• An alternative process implements the nMOS and
pMOS transistors in their own respective wells.
• The p-well and n-well are fabricated in a very lightly
doped epitaxial(epi) layer on the top of the p+ or n+
substrate. nMOST pMOST
n+ n+ p+ p+
p well n well
epi-layer
p+ or n+ type substrate
Twin-tub CMOS process
• The high dope of the n+ or p+ substrate is used to
prevent the latch-up problem.
• Each well can be optimized to yield the highest
performance for both type of transistors. This can be
done by minimizing source/drain junction capacitance
and body effect.
• Both wells are each others complement and can
formed using a single mask.
• Better scaling properties which facilitate rapid transfer
of a design from one process generation to another.
CMOS Devices
Single crystal Silicon Ingot, a wafer, Chip and a device
Silicon Wafer and Chips
This enlarged image of a grain of salt on a piece of a
microprocessor should give you an idea of how small
and complex a microprocessor really is.
IC Packaging
Requirements to package
• Protect circuit from external environment
• Protect circuit during production of PCB
• Mechanical interface to PCB
• Interface for production testing
• Good signal transfer between chip and PCB
• Good power supply to IC
• Cooling
• Small
• Cheap
Materials
• Ceramic
– Good heat conductivity
– Hermetic
– Expensive ( often more expensive than chip itself !)
• Metal (has been used internally in IBM)
– Good heat conductivity
– Hermetic
– Electrical conductive (must be mixed with other
material)
• Plastic
– Cheap
– Poor heat conductivity
Can be improved by incorporating metallic heat plate.
• Package types:
– Below 1 watt: Plastic
– Below 5 watt: Standard ceramic
– Up to 30 watt: Special
Passive heat sink Active heat sink Water cooled mainframe computer
Chip mounting
• Pin through hole
– Pins traversing PCB
– Easy manual mounting
– Problem passing signals between pins on PCB (All
layers)
– Limited density
• Surface Mount Devices (SMD)
– Small footprint on surface of PCB
– Special machines required for mounting
– No blocking of wires on lower PCB layers
– High density
Traditional packages
• DIL (Dual In Line)
• Low pin count
• Large
• PGA (Pin Grid Array)
• High pin count (up to 400)
• Previously used for most CPU’s
• PLCC (Plastic leaded chip carrier)
• Limited pin count (max 84)
• Large
• Cheap
• SMD
• QFP (Quarter Flat pack)
• High pin count (up to 300)
• small
• Cheap
• SMD
New package types
• BGA (Ball Grid Array)
• Small solder balls to connect Package inductance:
to board 1 - 5 nH
• small
• High pin count
• Cheap
• Low inductance
• CSP (Chip scale
Packaging)
• Similar to BGA
• Very small packages
New Transistor Structures
• Lateral Asymmetric Channel
• Silicon-on-Insulator (SOI)
• SiGe
• Metal Gate FET
• Single Electron Transistor
Silicon-on-Insulator (SOI)
• Active silicon on a thick insulator (SiO2)
• Mainstream technology of the future?
Silicon-on-insulator CMOS
• The CMOS processes require rather deep n-well and/or
p-well diffusion to achieve low threshold voltage (≈ 1V).
The resulting lateral diffusions necessitate relatively
large spacing between p and n type transistors.
• The resulting increase in IC area can be avoided. This
gives complete isolation of nMOS and pMOS transistors
removing the possibility of latch up.
nMOST pMOST
n+ p- n+ p+ n- p+
Isolating substrate
SOI Advantages
• Faster
• Latchup-proof
• Less short channel effects
• Better suited to low-voltage & low-power
needs
• More compact
• 3-D integration
But ...
• SOI wafers are expensive
• Floating body effects, eg “kink”
Lateral Asymmetric Channel (LAC)
Transistors
• Asymmetrically doped channel; heavier
doping near source
• Improved characteristics
– Better DIBL
– Velocity overshoot
– Improved hot-carrier performance
• Disadvantage: Design difficult
Fabrication - LAC Transistors
Boron
• E-beam lithography used to
define channel lengths down to
100 nm poly
• VT implant (tilted by 7-15 FOX FOX
degrees) for LAC devices done
after gate oxidation B
O
• Two-step Ti silicidation and Ge R
O
preamorphization to control N
silicide depth and reduce series S D
resistance
Silicon-on-Insulator (SOI) MOSFETs:
LAC and CON Devices
LAC Implant G
0.8
L = 0.1µm
TSOI = 35nm
0.6 Points LAC
S D Lines CON
(Vg - Vt)
1.4 V
Ids (A/µm)
0.4 1.15 V
Buried Oxide 0.9 V
0.65 V
0.2 0.4 V
Si substrate
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vds (V)
Vertical Replacement Gate
Transistor
Source NiSi