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CMOS Fabrication

Overview

Dr. Arvind Shaligram


Dept. of Electronic Science,
University of Pune, Pune-411 007
adshaligram@gmail.com
EARLY HISTORY (before 1800’s)

SLIDE RULE 1600’s


ABACUS

BLAISE PASCAL adding machine


LEIBNITS adding machine 1642
early 1700’s
Jacquard loom

It was not until the beginning of the 19th


century (1800’s) that the ideas automatic
computing machines began to evolve. The
first was developed by a French textile
manufacturer called Joseph Jacquard. He
invented a punch card system for
programming the designs on a carpet
making loom. First he used single cards to
control the pattern of the threads. On later
machines the cards were joined together to
form repeating patterns. This idea of punch
cards was adopted for use with musical
instruments, such as the barrel organ. Here
a sequence of valves were opened and closed
controlling air flow into various organ pipes.
Tunes could be programmed and loaded
into the machine.
BABBAGE difference engine

In the 1820’s Charles Babbage designed a


mechanical machine called the Difference engine.
The purpose of this machine was to calculate and
print out tables for the Admiralty. (ie, tides, tables
and planetary positions for navigation). The
machine consisted of cog wheels that could be set in
keyed positions, these turned as the computations
were performed. Due to the limitations of
mechanical engineering in this period, and lack of
money, the machine was never completed.
BABBAGE’S analytical engine
A mechanical computer that can solve any
mathematical problem. It used punch-cards
similar to those used by the Jacquard loom and
can perform simple conditional operations.

Babbage laid down the foundations for modern


computing. He stated that an automatic computing
machine must have:-

• A store for the numbers, we now call this


memory.
• A device for performing arithmetic operations,
he called this a mill, we now call this the
arithmetic unit or central processor unit (CPU).
3) A device for causing the operations of the
machine, for example transferring numbers from
one place to another. This is now referred to as
the control unit.
4) An input and output device. Such as card reader
or printer. Today this would also include screen,
mouse and keyboard.
ENIAC - The first electronic computer
(1946)
The Integrated Circuit
• 1959: Jack Kilby, working at TI, dreams
up the idea of a monolithic “integrated
circuit”
– Components connected by hand-soldered
wires and isolated by “shaping”, PN-diodes
used as resistors (U.S. Patent 3,138,743)
Diagram from patent application
Microelectronics is the art, science and
technology of designing and fabricating
integrated circuits with small-dimension
electronic devices
Moore’s Law
• In 1965, Gordon Moore predicted that transistors would
continue to shrink, allowing:
– Doubled transistor density every 18-24 months
– Doubled performance every 18-24 months
• History has proven Moore right
• But, is the end is in sight?
– Physical limitations
– Economic limitations

Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Image source: Intel Corporation www.intel.com
Moore’s Law
• Propounded by Gordon Moore in the 1960’s
• Predicts that the complexity of ICs increases
exponentially
• Caused by a steady decrease in minimum
feature size
• Produces increases in speed
• Moore’s Law is the reason microelectronics
has dramatically changed our lives in the last
three decades
Microelectronics
Technology
Micro Electronics

Inert Substrate Active Substrate


(Good Resistors)

Silicon GaAs
Fast
MOS Bipolar

N P CMOS TTL ECL


Current : Majority None thro’ gate Current : Majority + Minority
thro’ base
Silicon CMOS

• Si is the dominant technology, because


of silicon dioxide
- Other materials include GaAs, GaN, SiGe,
SiC for specialized applications
• CMOS is the dominant Si technology
because of area and power
- Bipolar important for niche applications
- more than 90% of all semiconductors
today are Si CMOS
CMOS: A Historical Perspective
• Field effect patented in 1930
• Failed effort to make a FET led to a Nobel-
prize winning invention in 1947 (Shockley,
Bardeen, Brattain)
• First working MOS transistors in the 1960’s
(Kahng)
• First MOS ICs in the early 1970’s –
calculators, memories (Intel)
CMOS: A Historical Perspective
(cont’d)
• First Microprocessor in 1973 (Shima)
• CMOS becomes the dominant
technology for VLSI in the late 1980’s
• Moore’s law ensures dominance of
silicon CMOS over all other
microelectronic technologies
• In 2000, there is a $200 billion
semiconductor industry
CMOS: A Historical Perspective
(cont’d)
• In 2001, state-of-the art microprocessor
has L = 0.18μm, tox = 2.5nm,
No. of transistors = 20 million, f =
1GHz
• In 2005, we have
L = 0.065μm, tox = 1.2nm,
No. of transistors = 100 million, f =
3GHz
• CMOS will be the dominant technology
at least up to 2020
IC Evolution
• ULSI – Ultra Large Scale Integration
(1990)
– 107 – 109
• Giga-Scale Integration (2005)
– 109 – 1011
• Tera-Scale Integration (2020)
– 1011 - 1013
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
1960
1961
1962

Electronics, April 19, 1965.


1963
1964
1965
1966
1967
1968
1969
1970
1971
Moore’s Law

1972
1973
1974
1975
Evolution in Complexity
Transistor Counts
1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Courtesy, Intel
Moore’s law in Microprocessors
1000

100 2X growth in 1.96 years!


Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Courtesy, Intel
Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel
Minimum Feature Size Trend

From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course


ITRS’98
(International Technology
Roadmap)
Year 1997 1999 2002 2005 2008 2011 2014
Dense 0.25 0.18 0.13 0.10 0.07 0.05 0.0035
lines:
Half
pitch(μm)
Shrink rate - 0.72 0.72 0.77 0.70 0.7 0.71
Isolated 0.20 0.14 0.10 0.07 0.05 0.03 0.025
lines: MPU 5
gate(μm)
Shrink rate - 0.70 0.71 0.70 0.71 0.70 0.70
DRAM @ 256M 1G 4G 16G 64G 256G 1T
introduction
DRAM @ 64M 256M 1G 4G 16G 64G 256G
production
Feature Size
•The ratio of minimum allowable value of gate width(W) and
gate
length(L) is called as minimum feature size.
•Thus feature size is function of IC technology.

N-MOSFET
layout
VLSI Tech: CMOS
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected
to VDD

Key feature: p transistor
transistor length L 2002: L=130nm
Polysilicon Gate
SiO2 2003: L=90nm
Insulator L D D
2005: L=65nm
W
Source Drain
G SB G
n+ n+
channel

p substrate S S
substrate connected
n transistor to GND
FABRICATION
PROCESS
Fabrication of MOS Transistor
The MOS fabrication process consists of
• Wafer preparation
• Several steps of photolithography
• Etching
• Oxidation
• Diffusion
• Ion Implantation
• Deposition
Diffusion
Ion Implantation
Deposition
Materials
• Single crystal silicon – SCS
– Anisotropic crystal
– Semiconductor, great heat conductor
• Polycrystalline silicon – polysilicon
– Mostly isotropic material
– Semiconductor
• Silicon dioxide – SiO2
– Excellent thermal and electrical insulator
– Thermal oxide, LTO, PSG: different names for different
deposition conditions and methods
• Silicon nitride – Si3N4
– Excellent electrical insulator
• Aluminum – Al
– Metal – excellent thermal and electrical conductor
Silicon properties
• Semiconductor
– Electrical conductivity varies over ~8 orders of
magnitude depending on impurity concentration (from
ppb to ~1%)
– N-type and P-type dopants both give linear
conduction, but from fundamentally different
mechanisms
– N-type touching P-type forms a diode
• Cubic crystal
– Diamond lattice
– Anisotropic mechanical properties
Periodic Table
Step 1: Obtaining the Sand
• The sand used to grow the wafers has to
be a very clean and good form of silicon.
• For this reason not just any sand scraped
off the beach will do.
• Most of the sand used for these processes
is shipped from the beaches of Australia.
FABRICATING SILICON
• Quartz, or Silica, Consists of Silicon Dioxide
• Sand Contains Many Tiny Grains of Quartz
• Silicon Can be Artificially Produced by
Combining Silica and Carbon in Electric
Furnice
• Gives Polycrystalline Silicon (multitude of
crystals)
• Practical Integrated Circuits Can Only be
Fabricated from Single-Crystal Material
Step 2: Preparing the Molten
Silicon Bath

• The sand is taken and put into a pot


where it is heated to about 1600
degrees C where it melts.
• The molten sand will become the
source that will ultimately produce the
raw poly-crystalline silicon.
Raw Polysilicon

• Raw polycrystalline silicon


produced by mixing refined
trichlorosilane with hydrogen
gas in a reaction furnace.
• The poly-crystalline silicon is
allowed to grow on the
surface of electrically heated
tantalum hollow metal wicks
Creating the Single Crystalline Ingot

• Crushed high-purity polycrystalline


silicon is doped with elements like
arsenic, boron, phosphorous or
antimony and melted at 1400° in a
quartz crucible surrounded by an inert
gas atmosphere of high-purity argon.
• The melt is cooled to a precise
temperature, then a "seed" of single
crystal silicon is placed into the melt
and slowly rotated as it is "pulled" out.
Step 3: Making the Ingot

• A pure silicon seed


crystal is now placed
into the molten sand
bath.
• This crystal will be
pulled out slowly as
it is rotated.
• The result is a pure
silicon tube that is
called an ingot
Creating the Single Crystalline Ingot
(cont.)
• The surface tension
between the seed and the
molten silicon causes a
small amount of the liquid
to rise with the seed and
cool into a single
crystalline ingot with the
same orientation as the
seed.
• The ingot diameter is
determined by a
combination of
temperature and
extraction speed
CYLINDER OF
MONOCRYSTALLINE

• The Silicon Cylinder is


Known as an Ingot
• Typical Ingot is About 1 or
2 Meters in Length
• Can be Sliced into
Hundreds of Smaller
Circular Pieces Called
Wafers
• Each Wafer Yields
Hundreds or Thousands of
Integrated Circuits
Ingot Sizes

• Most ingots produced


today are 150mm (6")
and 200mm (8")
diameter,
• For the most current
technology 300mm (12")
and 400mm (16")
diameter ingots are
being developed.
Ingot Characterization

• Single Crystal Silicon ingots are


characterized by the orientation of their
silicon crystals. Before the ingot is cut into
wafers, one or two "flats" are ground into
the diameter of the ingot to mark this
orientation.
Step 4: Preparing the Wafers
• The ingot is ground
into the correct
diameter for the
wafers.
• Then it is sliced into
very thin wafers.
• This is usually done
with a diamond saw.
WAFER MANUFACTURING
• The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw
into Thin Wafers
• Sorted by Thickness
• Damaged Wafers Removed During Lapping
• Etch Wafers in Chemical to Remove any Remaining Crystal
Damage
• Polishing Smoothes Uneven Surface Left by Sawing Process
Wafer Lapping
• The sliced wafers are
mechanically lapped
using a counter-rotating
lapping machine and
aluminum oxide
slurry.This flattens the
wafer surfaces, makes
them parallel and
reduces mechanical
defects like saw
markings
Wafer polishing
• Next, the wafers are
polished in a series of
combination chemical and
mechanical polish
processes called CMP
• The wafers are held in a
hard ceramic chuck using
either wax bond or vacuum
and buffed with a slurry of
silica powder, RO/DI water
and sodium hydroxide
Silicon wafer fabrication – slicing and
polishing
Some wafers in storage trays
Growth of Epitaxial Silicon
• The purpose of EPI growth is to create a layer
with different, usually lower, concentration of
electrically active dopant on the substrate.
For example, an n-type layer on a p-type
wafer.
• This layer is of a much better quality then the
slightly damaged or unclean layer of silicon in
the wafer
• It is called the Epitaxial layer - where the
actual processing will be done.
An Epitaxial reactor.
Oxidation, nitridation, metal and dielectric film
deposition is carried out for isolation and
interconnection

Diffusion and Ion implantation of impurities is done


for changing the dopant concentration and making
devices

Various patterned layers are created using


lithography and etching
The simplest method of producing an oxide layer
consists of heating a silicon wafer in an oxidizing
atmosphere.
Diffusion

Diffusion is often two step process -


The first step is called predeposition and comprises the
deposition of a high concentration of the required impurity.
The impurity penetrates some tengths of a micron into a
silicon at a temperature of 800 to 1200 deg. Silicon atoms
in the lattice are then substituted by impurity atoms.
The second step is drive-in diffusion. This high temperature
step decreases the surface impurity concentration and
forces the impurities to penetrate deeper in to the wafer.
Implantation
The ion implantation(doping in MOS process) takes
place in an ion implanter which comprises a vaccum
chamber and an ion source which can emit
phosphorous arsenic or boron ions.
Silicon wafers are placed in a vacuum chamber and the
ions are accelerated into the silicon under the
influence of electric and magnetic field. The
penetration depth depends on the ion energy.
Ion implantation is characterized by the following
parameters :
– the type of ions
– the accelerating voltage
– the current strength
– the implementation duration
Ion Implantation
Methods of planar process
• Diffusion • Ion Implantation
• A uniformly doped ingot is • A particle accelerator is
sliced into wafers. used to accelerate a
• An oxide film is then grown doping atom so that it
on the wafers. can penetrate a silicon
• The film is patterned and crystal to a depth of
etched using several microns
photolithography exposing
specific sections of the • Lattice damage to the
silicon. crystal is then repaired
• The wafers are then spun by heating the wafer at a
with an opposite polarity moderate temperature for
doping source adhering
a few minutes. This
only to the exposed areas.
process is called
• The wafers are then heated
annealing.
in a furnace (800-1250
deg.C) to drive the doping
atoms into the silicon.
Comparison of Diffusion and Ion
Implantation
• Diffusion is a cheaper and more simplistic method,
but can only be performed from the surface of the
wafers. Dopants also diffuse unevenly, and interact
with each other altering the diffusion rate.

• Ion implantation is more expensive and complex. It


does not require high temperatures and also allows
for greater control of dopant concentration and
profile. It is an anisotropic process and therefore
does not spread the dopant implant as much as
diffusion. This aids in the manufacture of self-
aligned structures which greatly improve the
performance of MOS transistors.
Deposition
The deposition is of thin layer of dielectric material,
polysilicon and metal. Most commonly used
dielectrics are silicon-dioxide and silicon-nitride.
Deposition occurs via a chemical process called
Chemical Vapour Deposition (CVD).
Si(OC2H5)4 -> SiO2 + by-products
3SiCl2H2 + 4NH3 -> Si3N4 + 6HCl + 6H2
The following reaction takes place during polysilicon
deposition
SiH4 -> Si + 2H2
Metal layers are deposited by means of both physical
and chemical methods. The physical methods are
evaporation and sputtering.
In sputtering, an aluminium target is bombarded with
argon ions and a flux of aluminium flows from target
to wafer surface.
Etching
There are several etching techniques:-
• Wet-etching: wafer is immersed in a chemical etching
liquid. The process is isotropic - etching rate is same in all
directions.
• Dry-etching: both physical and chemical processes are
used. The process is anisotropic - etching is limited to one
direction due to the perpendicular trajectory of the
employed ions at the wafer surface.
• Plasma-etching: wafers are immersed in a gaseous plasma
containing chlorine and fluorine ions that etch SiO2.
• Sputter-etching: wafer is bombarded with the by gas ions
such as Argon(Ar) which physically dislodge atoms at the
wafer surface.
Plasma Etchers
Photolithography
Photomasks and Reticles
Examples of 5X Reticles:
Photolithography
Photomasks and Reticles
Once the mask has been accurately aligned with the pattern
on the wafer's surface, the photoresist is exposed through the
pattern on the mask with a high intensity ultraviolet light.
There are three primary exposure methods: contact,
proximity, and projection.
Lithography
Pattern Transfer From
Mask To Wafer

mask
exposed
Photo resist layer
Si3N4
SiO2

WAFER

Removal
Development
Coverage
Exposed
Masking
of +
the
Etching
Wafer with
of
Photo
+
photo
of the
photo
exposure
the
Oxide photo
resist
resist
lacquer
nitride
(or resist
layer
Nitride)
Semiconductor Manufacturing Process
CMOS VLSI
CMOS Technology

As shown above PMOS transistor is formed in a separate n-type region


known as n-well.
Fabrication of CMOS
Devices
P-well and n-well

Technologies used for CMOS fabrications include

• N-well process
• P-well process
• Twin-tub process
• Silicon on insulator.
P-Wells and N-Wells
IN
P substrate N substrate
contact
G OUT G contact
D S

n+ n+ p+ p+
p+ n+

P-well N-well

• A p- transistor is built on an n- substrate and an n-


transistor
is built on a p-substrate
P-Wells and N-Wells
• In order to have both types of transistors on the same

substrate, the substrate is divided into “well” regions


(Shaded
region in the standard cells)
• Two types of wells are available - n- well and p- well
• In a p- substrate, an n- well is used to create a local
region of n
type Substrate, wherein the designer can create p-
transistors
• In a n- substrate, a p- well creates a local p- type
substrate
region, to accommodate the n- transistors.
• Hence, every p- device is surrounded by an n- well,
that must
P-well CMOS Process
• nMOS transistors are formed in a diffused
p-well
• pMOS and the p-well are formed in a n-
substrate. This requires the p-well doping
concentration much higher than that of the
substrate. nMOST pMOST

n+ n+ p+ p+
p

p-well
n-
P-well CMOS Process
•P-impurity level at the
bottom boundary of the p-
well is exactly equal to the n-
substrate doping
n-substrate
n+
concentration.
p-well
•The impurity concentration
n+ where the n-channel
transistors are formed at p-
z well surface is about 10 times
larger than the p-well bottom.
•The performance of the
nMOS transistor affected by
WELL
p-dope
lower mobility of holes,
relatively large source/drain
z capacitance and a large body-
SUBSTRATE
n-dope effect.
•Development and application
of pure p-well CMOS process
is stagnated totally.
N-Well CMOS Process
• Typical fabrication processes for n-well are similar
to that of p-well process except that n-well is
implanted rather than p-well.
• N–well CMOS circuits are superior to P-well
because of lower substrate bias effects on
transistor threshold voltage & inherently low
parasitic capacitance associated with source &
drain regions and also lower mobility of holes ( µ p ≈
µ n/3).
nMOST pMOST

n+ n+ p+ p+
n

n-well
p-
Twin-tub CMOS process
• One type of transistor is always affected by a low
performance due to the necessarily high dope of the
well in both the previous methods.
• An alternative process implements the nMOS and
pMOS transistors in their own respective wells.
• The p-well and n-well are fabricated in a very lightly
doped epitaxial(epi) layer on the top of the p+ or n+
substrate. nMOST pMOST

n+ n+ p+ p+
p well n well

epi-layer
p+ or n+ type substrate
Twin-tub CMOS process
• The high dope of the n+ or p+ substrate is used to
prevent the latch-up problem.
• Each well can be optimized to yield the highest
performance for both type of transistors. This can be
done by minimizing source/drain junction capacitance
and body effect.
• Both wells are each others complement and can
formed using a single mask.
• Better scaling properties which facilitate rapid transfer
of a design from one process generation to another.
CMOS Devices
Single crystal Silicon Ingot, a wafer, Chip and a device
Silicon Wafer and Chips
This enlarged image of a grain of salt on a piece of a
microprocessor should give you an idea of how small
and complex a microprocessor really is.
IC Packaging
Requirements to package
• Protect circuit from external environment
• Protect circuit during production of PCB
• Mechanical interface to PCB
• Interface for production testing
• Good signal transfer between chip and PCB
• Good power supply to IC
• Cooling
• Small
• Cheap
Materials
• Ceramic
– Good heat conductivity
– Hermetic
– Expensive ( often more expensive than chip itself !)
• Metal (has been used internally in IBM)
– Good heat conductivity
– Hermetic
– Electrical conductive (must be mixed with other
material)
• Plastic
– Cheap
– Poor heat conductivity
Can be improved by incorporating metallic heat plate.
• Package types:
– Below 1 watt: Plastic
– Below 5 watt: Standard ceramic
– Up to 30 watt: Special

Passive heat sink Active heat sink Water cooled mainframe computer
Chip mounting
• Pin through hole
– Pins traversing PCB
– Easy manual mounting
– Problem passing signals between pins on PCB (All
layers)
– Limited density
• Surface Mount Devices (SMD)
– Small footprint on surface of PCB
– Special machines required for mounting
– No blocking of wires on lower PCB layers
– High density
Traditional packages
• DIL (Dual In Line)
• Low pin count
• Large
• PGA (Pin Grid Array)
• High pin count (up to 400)
• Previously used for most CPU’s
• PLCC (Plastic leaded chip carrier)
• Limited pin count (max 84)
• Large
• Cheap
• SMD
• QFP (Quarter Flat pack)
• High pin count (up to 300)
• small
• Cheap
• SMD
New package types
• BGA (Ball Grid Array)
• Small solder balls to connect Package inductance:
to board 1 - 5 nH

• small
• High pin count
• Cheap
• Low inductance
• CSP (Chip scale
Packaging)
• Similar to BGA
• Very small packages
New Transistor Structures
• Lateral Asymmetric Channel
• Silicon-on-Insulator (SOI)
• SiGe
• Metal Gate FET
• Single Electron Transistor
Silicon-on-Insulator (SOI)
• Active silicon on a thick insulator (SiO2)
• Mainstream technology of the future?
Silicon-on-insulator CMOS
• The CMOS processes require rather deep n-well and/or
p-well diffusion to achieve low threshold voltage (≈ 1V).
The resulting lateral diffusions necessitate relatively
large spacing between p and n type transistors.
• The resulting increase in IC area can be avoided. This
gives complete isolation of nMOS and pMOS transistors
removing the possibility of latch up.
nMOST pMOST

n+ p- n+ p+ n- p+

Isolating substrate
SOI Advantages

• Faster
• Latchup-proof
• Less short channel effects
• Better suited to low-voltage & low-power
needs
• More compact
• 3-D integration
But ...
• SOI wafers are expensive
• Floating body effects, eg “kink”
Lateral Asymmetric Channel (LAC)
Transistors
• Asymmetrically doped channel; heavier
doping near source
• Improved characteristics
– Better DIBL
– Velocity overshoot
– Improved hot-carrier performance
• Disadvantage: Design difficult
Fabrication - LAC Transistors
Boron
• E-beam lithography used to
define channel lengths down to
100 nm poly
• VT implant (tilted by 7-15 FOX FOX
degrees) for LAC devices done
after gate oxidation B
O
• Two-step Ti silicidation and Ge R
O
preamorphization to control N
silicide depth and reduce series S D
resistance
Silicon-on-Insulator (SOI) MOSFETs:
LAC and CON Devices
LAC Implant G

0.8
L = 0.1µm
TSOI = 35nm
0.6 Points LAC
S D Lines CON
(Vg - Vt)
1.4 V

Ids (A/µm)
0.4 1.15 V
Buried Oxide 0.9 V
0.65 V
0.2 0.4 V

Si substrate
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vds (V)
Vertical Replacement Gate
Transistor

From J. M. Hergenrother et al., IEDM 1999, p.75


Shrink Transistors to 10nm or 30 Atoms
with UCB’s innovation, FinFET, and today’s
fab equipment
Gate Drain
Int’l Technology Roadmap
for Semiconductors
100

Source NiSi

GATE LENGTH (nm)


Poly-Si
220Å
SiO2 cap 10

Lg=10nm LOW POWER


Si Fin HIGH PERFORMANCE
1
BOX 2000 2005 2010 2015 2020
YEAR

UC-Berkeley collaboration with AMD.


2002 IEDM
From H.S.P.Wong, Sub-100 nm CMOS, IEDM 1999 Short Course
Expanding the Silicon Revolution
amplifier
• Ubiquitous low-cost electronics

• MEMS (micro machines, motors, resonator


pumps, sensors)

• Displays -- AMLCD, micro mirror, LCD-on-Si (LCOS)

• Photonics -- imagers, optical switches, III-V on Si

• Biochips -- DNA-chip, Enzyme-chip, drug delivery..

• Energy -- solar cells, battery replacement, power scavenger

• Nanoelelctronics -- carbon nanotubes, self-assembly

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