INPUT OUTPUT ORGANISATION

 PRESENTED BY :-

PRASHANT SHARMA
IO ARCHITECHTURE

A computer’s IO architecture is
its interface to the outside world .
This architecture is designed to
provide a means of controlling
interaction with outside world .
For this a pc has a set of io
modules . Each module interface
to system bus & control at least
one IO device .
PURPOSE OF IO
MODULE
 It solve difference between CPU &
each peripheral .
 Peripheral are electromechanical &
electromagnetical devices ; CPU is
electronic device . So a conversion of
signal value is required .
 Data transfer rate of peripheral is
much slower than CPU . So a method
of synchronization is required .
PURPOSE OF IO
MODULE
 Data code & format in peripheral
differs from that of CPU .
 Word length of data in peripheral
is different from CPU .
 Operating mode of peripheral are
different from each other & each
of them must be controlled .
FUNCTIONS OF IO
MODULES
 Interface to processor & memory
via system bus .
 Interface to one or more
peripheral devices by data links
IO COMMANDS
 CONTROL COMMAND to activate a
peripheral & inform it what to do .
 STATUS COMMAND to test
various status conditions of io
module .
 INPUT COMMAND to transfer data
word from io device to CPU .
 OUTPUT COMMAND to transfer
data from CPU to io device .
REQUIREMENTS FROM
IO MODULE
 Control & timing
 Processor communication

 Device communication

 Data buffering

 Error detection
CONTROL & TIMING
 Coordinating flow of traffic
between internal resources &
external devices
 Managing allocation of time to
each peripheral attached to it .
 PROCESSOR

COMMUNICATION
 Command decoding
 Data transfer

 Status reporting

 Address recognition
DATA BUFFERING

Storing data intermediately for

compensating :
 To eliminate wait state of
processor
 Slow speed of IO devices
ERROR DETECTION
 Detecting mechanical & electrical
malfunctioning of devices
 Detecting parity error

 Employing error correcting

techniques
PROGRAMMED

IO
PROGRAMMED I\O

PROGRAMMED IO operation are

the result of io instructions
written in program . Each data
item transfer is initiated by an
instruction in program.
when CPU encounter the io
instruction
It execute this by issuing a
command to IO module .
TRANSFER
REQUIREMENT

 A CPU instruction including an io

instruction to transfer data

between
device & CPU .
 Store instruction to transfer data
from
CPU to memory .
 Other instruction to verify that
HARDWARE REQUIRED
 Additional h\w required for to
support prog. Io data transfer is
 STATUS REGISTER to store
current status of io devices
 BUFFER REGISTER to hold data
temporarily till io device is ready
to accept data delivered by cpu .
HARDWARE REQUIRED
 DATA COUNTER to keep track of
no of words to be transferred
 POINTER to store current
memory
location into which next word is
to be
written
TRANSFER PROCESS
When a byte of data is available :
 IO device place it on io bus & enable
DATA
VALID line
 IO interface accept data into DATA
REGISTER & enable DATA ACCEPTED
line
& set FLAG in status register
 CPU check FLAG to determine if data
is
placed in DR by IO device ; by
checking
TRANSFER PROCESS
 If FLAG = 1, CPU read data from
DR & set FLAG =0
 When FLAG =0 interface disables
data accept line
INSTRUCTION
REQUIRED
 Read status instruction.
 Instruction to check flag bit

if FLAG =0 go to step 1
if FLAG =1 go to step 3
 Instruction to read Data
Register
Issue read command to IO module

Read status of IO module

Not
Ready
Check status Error

Read condition
y
Read word from IO module

Write word into memory

NO
Done

Next instruction
 TYPES
 MPU initiated unconditional IO
data transfer
 MPU initiated conditional (polled )
IO data transfer
LIMITATION OF PROG
IO
The processor have to wait for
along time for io module of
concern to be ready for reception
\ transmission of data . Processor
while waiting must interrogate
the status of io module . As a
result the level of performance of
entire system is degraded .
INTERRUPT

DRIVEN IO
INTERRUPT DRIVEN IO

In this case when processor

issues a command to IO , it then
continues with other work . When
The device is ready it sends an
interrupt to CPU &
CPU then do the transfer .
PROCESS

FOR PROCESSOR :
 Processor issues a command to IO
module
& get busy with other task .
 At the end of each instruction cycle , CPU

checks for interrupt

 When interrupt occurs , CPU process the
interrupt .then it resume its previous
process .
PROCESS

FOR IO MODULE :
 IO module receive a command from
processor & then proceed to read data
from required peripheral .
 Once data is in module’s DR , it
signals an interrupt to over a control
line .
 Module then waits for it’s data request
from CPU . when it occurs module
place data on data bus
INTERRUPT
PROCESSING
Device controller issues an interrupt

Processor finishes execution of present instruction

Cpu signal acknowledgement of interrupt

Cpu pushes PSW & PC onto STACK

Cpu loads new PC value based on interrupt

Save reminder of process state information
Process interrupt
Restore process state information
Restore old PSW and PC
Issue read command to IO module

Read status of IO module

Check status Error

Read condition
y
Read word from IO module

Write word into memory

NO
Done

Next instruction
TYPE OF INTERRUPT
 Vectored interrupt
Source that interrupt supply the
branch information to computer .
This
information is called interrupt
vector .

 Non vectored interrupt

The branch address is assigned
DESIGN ISSUE
 To determine which device issued
the interrupt .
 In case of multiple interrupts
deciding the priority .
IDENTIFYING DEVICE
 Multiple interrupt lines
 Software poll
 Daisy chain
 Parallel priority interrupt
 Bus arbitration
MULTIPLE INTERRUPT
LINES
There are multiple interrupt line
between processor & IO module
. But it is impractical to
dedicate more than a few bus
lines to interrupt lines .
SOFTWARE POLL

On interrupt CPU branches to an

interrupt service routine whose
job is to poll each IO module to
determine which device has
caused the interrupt
but it is disadvantageous as it is
time consuming , because CPU
has to poll each io module until
the required module is found .
DAISY CHAIN

All IO module share a common

interrupt line & a single interrupt
ACK line daisy chained . On
interrupt CPU sends INTACK .
This signal propagates through a
series of IO module until it gets
required one .
this technique is called vectored
interrupt .
PARELLEL PRIORITY
INTERRUPT
It uses a register whose bits are
set separately by interrupt signal
from each device . Priority is
established according to the
position of the bits
in the register .
BUS ARBITATION

It makes use of vectored interrupt

.
here an IO module must first
gain control of bus before it can
raise interrupt request line .thus
only one module can raise the
line at one time .
DMA
DMA

It stands for direct memory access .

When large amount of data is to be
transferred DMA technique is used .it
involves an additional module on
system bus . During DMA transfer
CPU is ideal & has no control over
memory bus . DMA takes over the
buses to manage the transfer
directly between IO devices &
memory
WHY NEED DMA
Programmed I/O & interrupt I/O requires

active participation of CPU

Any data transfer must traverse a path

through the processor.

Transfer speed ids limited by speed with

which CPU can test & service devices .

 Cpu is tied up in managing an io
transfer.
 A no of instructions must be executed
for
ADDRESS
REGISTER
DATA COUNT

DATA REGISTER

CONTROL LOGIC
DMA CONTROLLER
It contains the usual circuitry . In addition
to this It has :
ADDRESS LINES for direct communication
with memory
DATA COUNT REGISTER storing no of
words to transfer
ADDRESS REGISTER containing an
address to specify desired location in
memory
CONTROL REGISTER specifying mode of
transfer i.e. To read or write .
DMA TRANSFER
Peripheral device sends a DMA
request
DMA activates bus request to CPU

CPU activates bus grant for DMA

DMA puts value of address register

on address bus .
DMA sends ACKNOWLEDGEMENT
signal to peripheral device .
DMA TRANSFER
Peripheral puts a data word on data
bus
For each transfer DMA increases
address register & decreases data
count register
When data count register = 0 ,
DMA stops transfer & send interrupt
to CPU
Cpu in response to interrupt checks
 INPUT OF BLOCK OF
DATA

Issue read block command to IO moduleCPU ->DMA

INTERRUPT
Read status of IO module
DMA ->CPU

NEXT INSTRUCTION
MODE OF DMA
OPERATION

Continuous DMA \ DMA block

transfer

Cycle stealing

Interleaved \ multiplexed DMA

DMA BLOCK TRANSFER

A sequence of arbitrary length of

data is transferred in a single
continuous burst . The controller
halts the CPU .
This type of process halted DMA
can support highest io data
transmission rate . But here CPU
is inactivate for some time which
is undesirable in many high speed
CYCLE STEALING
It allows CPU to transfer one data word
at a time , after which it must return
the control to CPU . CPU hardly delays
for one memory cycle to allow CMA to
steal one memory cycle . CPU can
equipped with special cycle stretching
inputs which suspends CPU clock for a
few microsecond after receiving DMA
request signal . Clock suspension is
limited to small duration such that
internal data is not lost in CPU
employing dynamic circuit .
TRANSPARENT DMA

It employs cycle stealing in true

sense .
There are instructions where CPU
works on data stored in internal
register & does not require system
bus . Such cycle can be truly stolen
by DMA .CPU is equipped with
additional logic to deactivate DMA
cycle sealing mode after specified
no of bus cycle is used by DMA
MULTIPLEXED DMA

If main memory is almost twice

as fast as CPU , then CPU & DMA
accesses of memory can be
interleaved on alternate half cycle
of clock . DMA access memory
during first half of clock cycle &
CPU during second half .
it is a true transparent DMA
operation achieved at cost of high
speed memory .
MULTIPLEXED DMA
DMA CONFIGRATIONS
CPU

DDMA IO ------------ IO MEMORY

Single bus detached

DMA CPU
MEMORY DMA

IO IO IO

IO BUS
DMA CONFIGRATIONS

CPU

DMA DMA MEMORY

IO IO IO

Single bus integrate DMA

-IO
 IO
CHANNEL
IO CHANNEL

It has the ability to execute IO

instructions . In this mode CPU
does not execute the IO
instructions. Cpu instruct IO
channel to execute a program in
memory , which contain IO
instructions
TYPES

 SELECTOR CHANNEL

 MULTIPLEXER CHANNEL
CHANNEL COMMAND
WORDS
The instructions executed by IOP
are called channel command
word (CCW).
They are of three types :

 Data transfer instructions

 Branch instructions
 Io device control instructions