Types of Random Access Memories

Types of Random Access Memories

SDRAM
 RAM
• Memories provide storage for computers
Summary
• Memories are organized in words
– Selected by addresses
• SRAMs store data in latches
– Accessed by surrounding circuitry
• RAM waveforms indicate the control signals
needed for access
• Words in SRAMs are accessed with decoders
– Only one word selected at a time
 ROM
• Read-only memory can normally only be read
Overview
• Internal organization similar to SRAM
• ROMs are effective at implementing truth tables
– Any logic function can be implemented using ROMs
• Multiple single-bit functions embedded in a
single ROM
• Also used in computer systems for initialization
– ROM doesn’t lose storage value when power is
removed
 Read-Only Memory (ROM)
• An array of semiconductor devices
– diodes
– transistors
– field effect transistors
• 2N words by M bits
• Data can be read but not changed
– (normal operating conditions)
 Read-Only
• N input bits Memory (ROM)
• 2N words by M bits
• Implement M arbitrary functions of N variables
– Example 8 words by 5 bits:
A
ROM
3 Input B 8 words
Lines
C x 5 bits

F0 F 1 F2 F3 F4

5 Output Lines
 ROM Implementation
• ROM = "Read Only Memory"
– values of memory locations are fixed ahead of time
• A ROM can be used to implement a truth table
– if the address is m-bits, we can address 2m entries in
the ROM. 0 0 0 0 0 1 1
– ourm outputs aren the bits of data 00that
0 1 1 1 0 0
1 0 the
1 1 address
0 0 points
to. 0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 1 0 0 0 1
1 1 0 0 1 1 0
1 1 1 0 1 1 1
 ROM
Implementation
• Suppose there are 10 inputs
10 address lines (i.e., 210 = 1024 different
addresses)
• Suppose there are 20 outputs

• ROM is 210 x 20 = 20K bits (and a rather

unusual size)

• Rather wasteful, since lots of storage bits

– For functions, doesn’t take advantage of K-maps, other
minimization
 Read-Only
Each Memory
minterm of each function can(ROM)
be specified

3 Inputs A B C F0 F1 F 2 F 3 F 4
Lines
A 0 0 0 0 1 0 1 0
ROM 0 0 1 1 1 1 1 0
B 8 words 0 1 0 0 0 0 1 1
C x 5 bits 0 1 1 1 1 1 0 1
1 0 0 0 1 0 1 0
1 0 1 0 1 1 1 1
1 1 0 1 0 1 0 1
F0 F1 F2 F3 F4 1 1 1 1 1 0 1 0

5 Outputs Lines
 ROM Internal Structure
n Inputs
Lines

n bit .
..
.
Memory Array
. decoder
. 2n words x m bits

...

m Outputs Lines
 Inside the ROM
• Alternate view
– Each possible horizontal/vertical intersection
indicates a possible connection
• Or gates at bottom output the word selected
by the decoder (32 x 8)
 ROM Types
• MROM
– NMOS Type Access time 200ns
– CMOS type Access time 100ns
– 47256 32K x 8
• PROM
– Field Programmable ROM or OTP
– CMOS type access time 100-250ns
– 27256 32K x 8
• EPROM
– CMOS type access time 200ns
– Special voltage level for programming 10v-25v
– Erasing 15-20 minutes UV light exposure
– Write time 100µs/byte
– Bulk erase only
– High density and low cost
– 2764 8K x 8
 ROM Types
• EEPROM
– CMOS type access time 200ns
– Special voltage for programming 21v and reverse voltage for
erasing.
– Write time 5µs/byte
– Byte erase possible
– Low density, high cost and highly complex
– 2864 8K x 8
• Flash PROM
– CMOS type access time 120ns
– Both sector (512 byte) erase and bulk erase in milliseconds
possible.
– Write time 10µs/byte
– Average density and lower cost than EEPROM.
– 28256 32K x 8
MROM / PROM
MROM / PROM
 ROM Memory Array
m0=A’B’C’

m1=A’B’C

m2=A’BC’
A
3 to 8 m3=A’BC

B decoder m4=AB’C’

m5=AB’C
C
m6=ABC’

m7=ABC

F0 F1 F2 F3 F4
EEPROM / Flash PROM
Commercial EEPROM
EEPROM Programming
 SRAM DRAM ROM EEROM
Speed
Memory
Fastest
Type Comparisons
Slow (15ns min Varies Slow
(3ns min access time) (read – 100ns)
access time) Access modes (write –
speed up (DDR 4700ns)
Price Expensive SDRAM,
Cheapestetc.) Cheap Expensive

Volatili Erased on Erased on Indestructibl Non-volatile

ty Power off Power off e (may have
limits)
Uses 1. High- Large Program Any data that
speed memories for memory for needs to
memory computers special- persist after
2. Small purpose power off
memories systems
 ROM Example
Specify a truth table for a ROM
A Bwhich
C implements:
F G H
F = AB + A’BC’ 0 0 0
G = A’B’C + C’ 0 0 1
H = AB’C’ + ABC’ + A’B’C 0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 ROM Example
Specify a truth table for a ROM
A Bwhich
C implements:
F G H
F = AB + A’BC’ 0 0 0 0
G = A’B’C + C’ 0 0 1 0
H = AB’C’ + ABC’ + A’B’C 0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
 ROM Example
Specify a truth table for a ROM
A Bwhich
C implements:
F G H
F = AB + A’BC’ 0 0 0 0 1 0
G = A’B’C + C’ 0 0 1 0 1 1
H = AB’C’ + ABC’ + A’B’C 0 1 0 1 1 0
0 1 1 0 0 0
1 0 0 0 1 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 0
 Function Implementation

m0=A’B’C’

m1=A’B’C

m2=A’BC’
A
3 to 8 m3=A’BC

B decoder m4=AB’C’

m5=AB’C
C
m6=ABC’

m7=ABC

Each column is a new function

Note: two outputs unused! F G H
 ROM
• ROMs provide stable storage for data
Summary
• ROMs have address inputs and data outputs
– ROMs directly implement truth tables
• In normal use ROMs are read-only
– They are only read, not written
• ROMs are often used by computers to store
critical information
– Unlike SRAM, they maintain their storage after the
power is turned off
 PLD
Overview
• Programmable logic offers designers opportunity
to customize chips
• Programmable logic devices have a fixed logic
structure
• Programmable array logic contain AND-OR
circuits
– First introduced in early 1980’s
• Field programmable gate arrays (FPGAs) contain
small blocks that implement truth tables
– First introduced in 1985 (Xilinx Corporation)
• Software used to convert user designs to
programming information
 Roadmap

• PROM
• PLA
• PAL
• CPLD
• FPGA
 NRE and unit cost metrics

• Unit cost
– the monetary cost of manufacturing each copy of the system,
excluding NRE cost
• NRE cost (Non-Recurring Engineering cost)
– The one-time monetary cost of designing the system
• total cost = NRE cost + unit cost * # of units
• per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost

Vahid & Givargis

 PLD
• Programmable Logic Device (PLD):
– An integrated circuit chip that can be configured by end
use to implement different digital hardware
– Also known as “Field Programmable Device (FPD) “
• All layers already exist
– Designers can purchase an IC
– Connections on the IC are either created or destroyed to
implement desired functionality
– Field-Programmable Gate Array (FPGA) very popular
• Benefits
– Low NRE costs, almost instant IC availability
• Drawbacks
 PLD Advantages
• Short design time
Nonrecurring engineering cost• Less expensive at low
PLD volume
ASIC
Cost

Volume
 PLD Categorization
PLD

SPLD HCPL
Simple PLD HighD
Capacity PLD

PLA PAL
Programmable Logic Programmable Array Logic
Array

CPLD FPGA
Complex PLD Field Programmable Gate Array
 PLD Logic Capacity
• SPLD: about 200 gates
– PLA, PAL
• CPLD
– About 50 SPLD devices equivalent
– Altera MAX7000 (5K logic gates)
– Altera MAX (9K logic gates)
– Xilinx XC9500
• FPGA
– Evolved from Mask-Programmable Gate Array
(MPGA) in which customization is done during chip
fabrication.
– Xilinx Vertex-E ( 3 million logic gates)
 Electrically Erasable PLDs
• Conventional PLDs are either
– One-time programmable
• –EEUV Erasable
PLDs can be programmed and erased in place
• Must
• A be placed
small (fourin a programmer
wire) toaprogram
connection to computer them
is
needed
• Once programmed, will retain program indefinitely
• Never have to take the chip out of its circuit
 Programmable ROM (PROM)

N input 2
N
xM M output
ROM

• Address: N bits; Output word: M bits

N
• ROM contains 2 words of M bits each

• The input bits decide the particular word that becomes availabl
on output lines
Logic Diagram of 8x3 PROM

Sum of minterms
Combinational Circuit Implementation
I0 I1 I2 F0 F1using
F2 PROM
0 0 0 1 0 0
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 0 1
1 1 0 1 0 0
1 1 1 0 1 0 F0 F1 F2
 PROM Types
• Programmable PROM
– Break links through current pulses
– Write once, Read multiple times
• Erasable PROM (EPROM)
– Program with ultraviolet light
– Write multiple times, Read multiple times
• Electrically Erasable PROM (EEPROM)/ Flash
Memory
– Program with electrical signal
– Write multiple times, Read multiple times
 PROM: Advantages and
Disadvantages
• Widely used to implement functions with
large number of inputs and outputs
• Design of control units (Micro-programmed
control units)
• For combinational circuits with lots of don’t
care terms, PROM is a wastage of logic
resources
 Programmed Array Logic (PAL)
C B A
Fusable links Fusable links – Links may be
“blown”. Once blown, they are
permanently open.
12V
+ -
F1
Current

Complex wiring is replaced with

programming

F2

PALs support multiple functions

of the same inputs

C’ C B’ B A’ A
 PAL Example
C B A
Program F1=A’B’+A’C

Blow all unused links

A’B’
F1

A’C
Program F2=A’BC

A’BC Leave unused product

F2 terms alone (AA’BB’CC’)

C’ C B’ B A’ A
Schematic Representation
x’s mark Connections – Fuses
D C B A
of PALs
are not blown

DC

D’C’
F1=DC + D’C’ + BA’ + B’A
BA’

B’A

DA

CB’
F2=DA + CB’ + D’C’BA
D’C’BA
0
x1 x2 x3
• Programmable Array Logic
(PAL)
– The AND gates are
P1 programmable, but the OR
gates are fixed.
f1
P2

P3

f2
P4

AND plane An example of a PAL

 Programmable Array Logic
(PAL)
• Programmable AND array
• Fixed OR array
– Each output line permanently connected to a specific
set of product terms
• Number of product terms per output > number of
product terms in each sum-of-product expression
• No sharing of product terms between outputs
• Number of switching functions that can be
implemented with PAL are more limited than
PROM and PLA
 Programmable Array
– Implements sum-of-
Logic
products expressions
x
– Four external inputs
(and complements)
– Feedback path from x
output F1
– Product term
connections made via
switches
 Programmable Array
– Consider implementing the
following expressionLogic x x x
x xx
x x

• I1 I2 I3 + I2 ‘ I 3 ‘ I4 + I 1 I4 = F 1

– Note that only functions of

up to three product terms can
be implements
• Larger functions need to be
chained together via the
feedback path
 The Way Things Are: Real PALs
Tristate
Buffer
2

Input pin
I/O pin
4

Vcc

Input pin GND

Output Inversion Ctrl

 A More GeneralProgrammable
Programmed Array Logic Idea Logic Array

A PAL has limits on the

arrangement of its sum-of-
products groupings. A PLA has complete
flexibility of its sum-of-
products groupings.
 1 2 n • Programmable Logic Array
(PLA)
Input buffers
– A collection of AND gates
and
inverters
that feeds a set of OR gates
– The inputs to each gate are
x1 x1 xn xn
programmable.
P1

AND plane OR plane

Pk

General structure of a PLA

f1 fm
PLA 4 X 6 X 2
Logic Implementation with PLA
• Finite number of AND gates => simplify
function to minimum number of product
terms
• Number of literals in a product term is not
important since we have all the input
variables
• Sharing of product terms between outputs
=> multiple-output minimization
Design with PLA
 1 2 3
x x x

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

Gate-level diagram of a PLA f1 f2

x1 x2 x3

OR plane
P1

P2

P3

P4

AND plane

Customary schematic of a PLA

f1 f2
 Sharing Product Terms in a PLA
D C B A
F = ABC + AD + AD
ABC G =ABC + ABC + AD
H =ABC + BD
ABC
J = B + AD
AD

AD

BD

F G H J
•
Programming
PLAs and PALs are
Devices
programmed using a
special programmer
• Most devices are erasable
• Don’t use fuses, but
instead electrical methods
of programming
• Erased by exposing to UV
light