VLSI

BHASKER REDDY k VLSI ppts for M.Tech and B.
Tech 1
UNIT::II::Topics
Layouts for logic networks.
Channel routing.
Simulation.
BHASKER REDDY k VLSI ppts for M.Tech and B.Tech 2
Standard cell layout
Layout made of small cells: gates,
flip-flops, etc.
Cells are hand-designed.
Assembly of cells is automatic:
cells arranged in rows;
wires routed between (and through)
cells.
Standard cell structure
VDD
VSS
n tub
p tub
Intra-cell wiring
pullups
pulldowns
pin
pin
F
e
e
d
t
h
r
o
u
g
h

a
r
e
a

Standard cell design
Pitch: height of cell.
All cells have same pitch, may have
different widths.
VDD, VSS connections are designed
to run through cells.
A feedthrough area may allow wires
to be routed over the cell.
Single-row layout design
Routing channel
cell cell cell cell cell
cell cell cell cell cell
wire Horizontal track
Vertical track
height
Routing channels
Tracks form a grid for routing.
Spacing between tracks is center-to-
center distance between wires.
Track spacing depends on wire layer
used.
Different layers are (generally) used
for horizontal and vertical wires.
Horizontal and vertical can be routed
relatively independently.
Routing channel design
Placement of cells determines
placement of pins.
Pin placement determines difficulty of
routing problem.
Density: lower bound on number of
horizontal tracks needed to route the
channel.
Maximum number of nets crossing from
one end of channel to the other.
Pin placement and routing
before
a b c
b c a
before
a b c
b c a
Density = 3
Density = 2
Example: full adder layout
Two outputs: sum, carry.
sum
carry
x1
x2
n1
n2
n3
n4
Layout methodology
Generate candidates, evaluate area
and speed.
Can improve candidate without starting
from scratch.
To generate a candidate:
place gates in a row;
draw wires between gates and primary
inputs/outputs;
measure channel density.
A candidate layout
x1 x2 n1 n2 n3 n4
a
b
c
s
cout
Density = 5
Improvement strategies
Swap pairs of gates.
Doesnt help here.
Exchange larger groups of cells.
Swapping order of sum and carry groups
doesnt help either.
This seems to be the placement that
gives the lowest channel density.
Cell sizes are fixed, so channel height
determines area.
Left-edge algorithm
Basic channel routing algorithm.
Assumes one horizontal segment per
net.
Sweep pins from left to right:
assign horizontal segment to lowest
available track.
Example
A B C
A B B C
Limitations of left-edge
algorithm
Some combinations of nets require
more than one horizontal segment
per net.
B A
A B
aligned
?
Vertical constraints
Aligned pins form vertical constraints.
Wire to lower pin must be on lower
track; wire to upper pin must be above
lower pins wire.
B A
A B
Dogleg wire
A dogleg wire has more than one
horizontal segment.
B A
A B
Rats nest plot
Can be used to judge placement
before final routing.
Simulation
Goals of simulation:
functional verification;
timing;
power consumption;
testability.
Types of simulation
Circuit simulation:
analog voltages and currents.
Timing simulation:
simple analog models to provide timing
but not detailed waveforms.
Switch simulation:
transistors as semi-ideal switches.
Types of simulation, contd.
Gate simulation:
logic gates as primitive elements.
Models for gate simulation:
zero delay;
unit delay;
variable delay.
Fault simulation:
models fault propagation (more later).
Example: switch simulation
a
+
+
b
c
d
c
1
0
0
X
X
X
o
0
1
1
Example, contd.
a
+
+
b
c
d
c
1
0
0
0
1
1
o
0
1
0
0
Topics
Combinational network delay.
Logic optimization.
Sources of delay
Gate delay:
drive;
load.
Wire:
lumped load;
transmission line.
Fanout
Fanout adds capacitance.
source
sink
sink
sink
Ways to drive large fanout
Increase sizes of driver transistors.
Must take into account rules for
driving large loads.
Add intermediate buffers. This may
require/allow restructuring of the
logic.
Buffers
Wire capacitance
Use layers with lower capacitance.
Redesign layout to reduce length of
wires with excessive delay.
Placement and wire capacitance
unbalanced load
more balanced
dvr
g1
g2
g3
g4
dvr
g1
g2
g3
g4
Path delay
Combinational network delay is
measured over paths through
network.
Can trace a causality chain from
inputs to worst-case output.
Path delay example
network
graph model
Critical path
Critical path = path which creates
longest delay.
Can trace transistions which cause
delays that are elements of the
critical delay path.
Delay model
Nodes represent gates.
Assign delays to edgessignal may
have different delay to different sinks.
Lump gate and wire delay into a
single value.
Critical path through delay
graph
Reducing critical path length
To reduce circuit delay, must speed
up the critical pathreducing delay
off the path doesnt help.
There may be more than one path of
the same delay. Must speed up all
equivalent paths to speed up circuit.
Must speed up cutset through critical
path.
False paths
Logic gates are not simple nodes
some input changes dont cause
output changes.
A false path is a path which cannot be
exercised due to Boolean gate
conditions.
False paths cause pessimistic delay
estimates.
Logic rewrites
deep logic
shallow
logic
Logic transformations
Can rewrite by using subexpressions.
Flattening logic increases gate fanin.
Logic rewrites may affect gate
placement.
False path example
Logic optimization
Logic synthesis programs transform
Boolean expressions into logic gate
networks in a particular library.
Optimization goals: minimize area,
meet delay constraint.
Technology-independent
optimizations
Works on Boolean expression
equivalent.
Estimates size based on number of
literals.
Uses factorization, resubstitution,
minimization, etc. to optimize logic.
Technology-independent phase uses
simple delay models.
Technology-dependent
optimizations
Maps Boolean expressions into a
particular cell library.
Mapping may take into account area,
delay.
May perform some optimizations on
addition to simple mapping.
Allows more accurate delay models.
Topics
Transistor sizing:
Spice analysis.
Logical effort.
Transistor sizing
Not all gates need to have the same
delay.
Not all inputs to a gate need to have
the same delay.
Adjust transistor sizes to achieve
desired delay.
Example: adder carry chain
+
+
a
i

b
i

a
i

c
i

b
i

c
i

b
i

a
i

b
i

a
i

c
i+1

One stage:
Carry chain optimization
Connect four stages.
Optimize delay through carry chain by
selecting transistor sizes.
Case 1
W/L for all stages: n = 0.75/0.5, p = 1.5/0.5
Case 2
Wider pulldowns for first stage XOR, larger first stage inverter:
Case 3
Larger transistors in second and third stages:
Inter-stage effects in transistor
sizing
Increasing a gates drive also
increases the load to the previous
stage:
Larger
drive
Larger
load
Logical effort
Logical effort is a gate delay model
that takes transistor sizes into
account.
Allows us to optimize transistor sizes
over combinational networks.
Isnt as accurate for circuits with
reconvergent fanout.
Logical effort gate delay model
Gate delay is measured in units of
minimum-size inverter delay t.
Gate delay formula:
d = f + p.
Effort delay f is related to gates load.
Parasitic delay p depends on gates
structure.
Effort delay
Effort delay has two components:
f = gh.
Electrical effort h is determined by
gates load:
h = C
out
/C
in

Logical effort g is determined by
gates structure.
Logical effort
1 input 2 inputs 3 inputs 4 inputs n inputs
inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
mux 2 2 2 2

Logical effort along a path
Logical effort along a chain of gates:
G = H g
i
.

Total electrical effort along path
depends on ratio of first and last
stage capacitances:
H = C
out
/C
in
.
Branching effort
Takes into account fanout.
Branching effort at one stage:
b = (C
onpath
+ C
offpath
/ C
onpath
)
Branching effort along path:
B = H b
i
.
Path delay
Path effort:
F = GBH.
Path delay is sum of delays of gates
along the path:
D = E g
i
h
i
+ E p
i
= D
F
+ P.
Sizing the transistors
Optimal buffer chains are
exponentially tapered:
f^ = F
1/N
.
Determine W/L of each gate on path
by working backward from the last
gate:
C
in,i
= g
i
C
out,
i / f^
Example: logical effort
Size transistors in a chain of three
two-input NAND gates.
First NAND is driven by minimum-size
inverter.
Last NAND is connected to 4X inverter.
Example, contd.
Logical effort G = 4/3 * 4/3 * 4/3.
Branching effort = 1.
Electrical effort = 4.
F = G B H = 9.5.
Optimum effort per stage f^ = 2.1.
Topics
Interconnect design.
Crosstalk.
Power optimization.
Interconnect
Even assuming logic structure is
fixed, we can:
change wire topology;
resize wires;
add buffers;
size transistors.
Multipoint nets
Two-point nets are easy to design.
Multipoint nets are harder:
How do we connect all the pins using
two-point connections?
Styles of wiring trees
source
sink 2
sink 1
Spanning tree
Steiner tree
Steiner point
Sized Steiner tree
source
sink 2
sink 1
Feeds both branches
Smaller currents in each branch
Buffer insertion in wiring trees
More complex than placing buffers
along a transmission line:
complex topology;
unbalanced trees;
differing timing requirements at the
leaves.
Van Ginneken algorithm
Given:
placements of sources and sinks;
routing of wiring tree.
Place buffers within tree to minimize
the departure time at the source to
meet all the sink arrival times:
T
source
= min
i
(T
i
-D
i
)
T
i
= arrival time at node i, D
i
= delay to
node I.
Delay calculation
Use Elmore model to compute delay
along path from source to sink.
Recursive delay calculation
Recursively compute Elmore delay
through the tree.
Start at sinks, work back to source.
r, c are unit resistance/capacitance of
wire.
L
k
is total capacitive load of subtree
rooted at node k.
Modifying the tree
Add a wire of length l at node k:
T
k
= T
k
- r/L
k
- 0.5rcl.
L
k
= L
k
+ cl.
Buffer node k:
T
k
= T
k
- D
buf
- R
buf
L
k
.
L
k
= C
buf
.
Join two subtrees m and n at node k:
T
k
= (T
m
, T
n
).
L
k
= L
m
+ L
n
.
Crosstalk
Capacitive coupling introduces
crosstalk.
Crosstalk slows down signals to static
gates, can cause hard errors in
storage nodes.
Crosstalk can be controlled by
methodological and optimization
techniques.
Coupling and crosstalk
Crosstalk current depends on
capacitance, voltage ramp.
w1 w2
C
c
i
c
t
Crosstalk analysis
Assume worst-case voltage swings,
signal slopes.
Measure coupling capacitance based
on geometrical alignment/overlap.
Some nodes are particularly sensitive
to crosstalk:
dynamic;
asynchronous.
Coupling situations
sig1
a x r
better
worse
bus[0]
bus[1]
bus[2]
Layer-to-layer coupling
Long parallel runs on adjacent layers
are also bad.
bus[0]
siga
SiO
2
Methodological solutions
Add ground wires between signal
wires:
coupling to V
SS
, a stable signal,
dominates;
can use V
SS
to distribute power, so long
as power line is relatively stable.
Extreme caseadd ground plane.
Costs an entire layer, may be overkill.
Ground wires
V
SS
sig1
V
SS
sig2
V
SS
Crosstalk and signal routing
Can route wires to minimize required
adjacency regions.
Take advantage of natural holes in
routing areas to decouple signals.
Minimizes need for ground signals.
Crosstalk routing example
Channel:
Assumptions
Take into account coupling only to
wires in adjacent tracks.
Ignore coupling of vertical wires.
Assume that coupling/crosstalk is
proportional to adjacency length.
Bad routing
Good routing
Crosstalk analysis
Want to estimate delays induced by
crosstalk.
Effect of coupling capacitance C
c

depends on relative transitions.
Aggressor changes, victim does not: C
c
.
Aggressor, victim move in opposite
directions: 2C
c
.
Aggressor, victim move in same
direction: 0.
Crosstalk analysis, contd.
Coupling effects depend on relative
switching time of nets.
Must use iterative algorithm to solve
for coupling capacitances and delays.
Power optimization
Glitches cause unnecessary power
consumption.
Logic network design helps control
power consumption:
minimizing capacitance;
eliminating unnecessary glitches.
Glitching example
Gate network:
Glitching example behavior
NOR gate produces 0 output at
beginning and end:
beginning: bottom input is 1;
end: NAND output is 1;
Difference in delay between
application of primary inputs and
generation of new NAND output
causes glitch.
Adder chain glitching
bad
good
Explanation
Unbalanced chain has signals arriving
at different times at each adder.
A glitch downstream propagates all
the way upstream.
Balanced tree introduces multiple
glitches simultaneously, reducing
total glitch activity.
Signal probabilities
Glitching behavior can be
characterized by signal probabilities.
Transition probabilities can be
computed from signal probabilities if
clock cycles are assumed to be
independent.
Some primary inputs may have non-
standard signal probabilities control
signal may be activated only
occasionally.
Delay-independent probabilities
Compute output probabilities of
primitive functions:
P
NOT
= 1 - P
in

P
OR
= 1 - H(1 P
i
)
P
AND
= H P
i

Can compute output probabilities of
reconvergent fanout-free networks by
traversing tree.
Delay-dependent probabilities
More accurate estimation of glitching.
Glitch accuracy depends on accuracy
of delay model.
Can use simulation-style algorithms
to propagate glitches.
Can use statistical models coupled
with delay models.
Power estimation tools
Power estimator approximates power
consumption from:
gate network;
primary input transition probabilities;
capacitive loading.
May be switch/logic simulation based
or use statistical models.
Factorization for low power
Proper factorization reduces glitching.
bad good
Factorization techniques
In example, a has high transition
probability, b and c low probabilities.
Reduce number of logic levels
through which high-probability signals
must travel in order to reduce
propagation of glitches.
Layout for low power
Place and route to minimize
capacitance of nodes with high
glitching activity.
Feed back wiring capacitance values
to power analysis for better
estimates.
Topics
Switch networks.
Combinational testing.
Boolean functions and switches
pseudo-AND
pseudo-OR
Driving switch outputs
If switch network output is not
connected to power supply through
switch path, output will float.
Switch network inputs may be
connected to power supply or logic
signals.
Switching logic signals
b
a
b
a
ab + ab
Switch multiplexer
Charge sharing
Interior nodes in a switch network
may not be driven.
Charge can accumulate on small
parasitic capacitances.
Shared charge can produce erroneous
output values.
Charge division
At undriven nodes, charge is divided
according to capacitance ratio.
Charge sharing example
Long chains of switches have
intermediate nodes which may be
disconnected from power supplies.
C
ab
C
ia
C
bc
Charge over time
time i C
ia
a C
ib
b C
bc
c C
0 1 1 1 1 1 1 1 1
1 0 0 1 0 0 1 0 1
2 0 0 0 1/2 1 1/2 0 1
3 0 0 0 1/2 0 3/4 1
3/4
4 0 0 0 0 0 3/4 0
3/4
5 0 0 0 3/8 1 3/8 0
3/4
Avoiding charge sharing
Make sure that for every input
combination there is a path from the
power supply to the output.
Manufacturing testing
Errors are introduced during
manufacturing.
Testing verifies that chip corresponds
to design.
Varieties of testing:
functional testing;
performance testing (binning chips by
speed).
Testing also weeds out infant
mortality.
Testing and faults
Fault model:
possible locations of faults;
I/O behavior produced by the fault.
Good news: if we have a fault model,
we can test the network for every
possible instantiation of that type of
fault.
Bad news: it is difficult to enumerate
all types of manufacturing faults.
Stuck-at-0/1 faults
Stuck-at-0/1: logic gate output is
always stuck at 0 or 1, independent
of input values.
Correspondence to manufacturing
defects depends on logic family.
Experiments show that 100% stuck-
at-0/1 fault coverage corresponds to
high overall fault coverage.
Testing procedure
Testing procedure:
set gate inputs;
observe gate output;
compare fault-free and observed gate
output.
Test vector: set of gate inputs applied
to a system.
Stuck-at faults in gates
a b OK SA0 SA1
0 0 1 0 1
0 1 1 0 1
1 0 1 0 1
1 1 0 0 1
a b OK SA0 SA1
0 0 1 0 1
0 1 0 0 1
1 0 0 0 1
1 1 0 0 1
NAND
NOR
Testing single gates
Three ways to test NAND for stuck-
at-0, only one way to test it for stuck-
at-1.
Three ways to test NOR for stuck-at-
1, only one way to test it for stuck-at-
0.
Testing combinational networks
100% coverage: test every gate for
stuck-at-0;
stuck-at-1.
Assume that there is only one faulty
gate per network.
Most networks require more than one
test vector to test all gates.
Multiple test example
Example
Can test both NANDs for stuck-at-0
simultaneously (abc = 000).
Cannot test both NANDs for stuck-at-
1 simultaneously due to inverter.
Must use two vectors.
Must also test inverter.
Stuck-at-open/closed model
Models transistors always on/off.
Stuck-open behavior
If t
1
is stuck open (switch cannot be
closed), there can be no path from
V
DD
to output capacitance.
Testing requires two cycles:
must discharge capacitor;
try to operate t
1
to see if capacitor can
be charged.
Delay fault
Delay falls outside acceptable limits:
gate delay fault assumes that all delays
are lumped into one gate;
path delay fault models delay problems
along path through network.
Delay problems reduce yield:
performance problems;
functional problems in some types of
circuits.
Combinational network testing
Two parts to testing:
controlling the inputs of (possibly
interior) gates;
observing the outputs of (possibly
interior) gates.
Combinational testing example
Testing procedure
Goal: test gate D for stuck-at-0 fault.
First step: justify 0 values on gate
inputs.
Work backward from gate to primary
inputs:
w1 = 0 (A output = 0);
i1 = i2 = 1.
Testing procedure, contd
Observe the fault at a primary output:
o1 gives different values if D is true/faulty.
Work forward and backward:
Fs other input must be 0 to detect true/fault.
Justify 0 at Es output.
In general, may have to propagate fault
through multiple levels of logic to primary
outputs.
Fault masking
Redundant logic can mask faults:
Redundancy example
Testing NOR for SA0 requires setting
both inputs to 0.
Network topology ensures that one
NOR input will always be 1.
Function reduces to 0:
f = (ab) + b = a + b + b = 0.
Redundancies and testing
Redundant logic cannot be controlled.
Observations requiring control of
redundant logic may not be possible.
Redundant logic should be minimized
to eliminate redundancy.
Redundancies can introduce delay
faults and other problems.
UNIT::3::Topics
Memory elements.
Basics of sequential machines.
Memory elements
Stores a value as controlled by clock.
May have load signal, etc.
In CMOS, memory is created by:
capacitance (dynamic);
feedback (static).
Variations in memory elements
Form of required clock signal.
How behavior of data input around
clock affects the stored value.
When the stored value is presented to
the output.
Whether there is ever a combinational
path from input to output.
Memory element terminology
Latch: transparent when internal
memory is being set from input.
Flip-flop: not transparentreading
input and changing output are
separate events.
Clock terminology
Clock edge: rising or falling transition.
Duty cycle: fraction of clock period for
which clock is active (e.g., for active-
low clock, fraction of time clock is 0).
Memory element parameters
Setup time: time before clock during
which data input must be stable.
Hold time: time after clock event for
which data input must remain stable.
clock
data
Dynamic latch
Stores charge on inverter gate
capacitance:
Latch characteristics
Uses complementary transmission
gate to ensure that storage node is
always strongly driven.
Latch is transparent when
transmission gate is closed.
Storage capacitance comes primarily
from inverter gate capacitance.
Latch operation
| = 0: transmission gate is off,
inverter output is determined by
storage node.
| = 1: transmission gate is on,
inverter output follows D input.
Setup and hold times determined by
transmission gatemust ensure that
value stored on transmission gate is
solid.
Stored charge leakage
Stored charge leaks away due to
reverse-bias leakage current.
Stored value is good for about 1 ms.
Value must be rewritten to be valid.
If not loaded every cycle, must
ensure that latch is loaded often
enough to keep data valid.
Stick diagram
| |
V
DD
V
SS
D
Q
Layout
D Q
V
DD
V
SS
| |
Multiplexer dynamic latch
Non-dynamic latches
Must use feedback to restore value.
Some latches are static on one phase
(pseudo-static)load on one phase,
activate feedback on other phase.
Recirculating latch
Static on one phase:
Clocked inverter
symbol
circuit
Clocked inverter operation
| = 0: both clocked transistors are
off, output is floating.
| = 1: both clocked inverters are onn,
acts as an inverter to drive output.
Clocked inverter latch
Regenerative latch
+
+
+
|
in
out
Clocked inverter latch operation
| = 0: i1 is off, i2-i3 form feedback
circuit.
| = 1: i2 is off, breaking feedback; i1
is on, driving i3 and output.
Latch is transparent when | = 1.
Flip-flops
Not transparentuse multiple storage
elements to isolate output from input.
Major varieties:
master-slave;
edge-triggered.
Master-slave flip-flop
|
D Q
master slave
Master-slave operation
| = 0: master latch is disabled; slave
latch is enabled, but master latch
output is stable, so output does not
change.
| = 1: master latch is enabled,
loading value from input; slave latch
is disabled, maintaining old output
value.
Sequential machines
Use memory elements to make
primary output values depend on
state + primary inputs.
Varieties:
Mealyoutputs function of present state,
inputs;
Mooreoutputs depend only on state.
Sequential machine definition
Machine computes next state N,
primary outputs O from current state
S, primary inputs I.
Next-state function:
N = o(I,S).
Output function (Mealy):
O = (I,S).
FSM structure
Constraints on structure
No combinational cycles.
All components must have bounded
delay.
Signal skew
Machine data signals must obey setup
and hold timesavoid signal skew.
Clock skew
Clock must arrive at all memory
elements in time to load data.
Topics
Clocking disciplines.
Flip-flop-based sequential
machines
Flip-flop rules
Primary inputs change after clock (|)
edge.
Primary inputs must stabilize before
next clock edge.
Rules allow changes to propagate
through combinational logic for next
cycle.
Flip-flop outputs hold current-state
values for next-state computation.
Signals in flip-flop system
positive clock edge
Latch-based machines
Latches do not cut combinational
logic when clock is active.
Latch-based machines must use
multiple ranks of latches.
Multiple ranks require multiple phases
of clock.
Two-sided latch constraint
Latch must be open less than the
shortest combinational delay.
Period between latching operations
must be longer than the longest
combinational delay.
Note: difference between shortest
and longest combinational delay may
be large (sum
0
vs. sum
31
).
Latch shoot-through
Latch may allow data to shoot through:
Strict two-phase clocking
discipline
Strict two-phase discipline is
conservative but works.
Can be relaxed later with proper
knowledge of constraints.
Strict two-phase machine makes
latch-based machine behave more
like flip-flop design, but requires
multiple phases.
Strict two-phase architecture
Two-phase clock
Phases must not overlap:
non-overlap region
Why it works
Each phase has a one-sided
constraint: phase must be long
enough for all combinational delays.
If there are no combinational loops,
phases can always be stretched to
make that section of the machine
work.
Total clock period depends on sum of
phase periods.
Clocking types
Logic on different phases operate at
different timescant mix signals
from different phases.
Primary inputs must obey the same
rules as internal signals.
Clocking types are bookkeeping that
help us ensure that machine structure
is valid.
Stable signals
A logic signal is always stable during
one phasephase in which the latch
which produced it is not active.
Easiest to think of machine behavior
in terms of stable signals, though
signals propagate while not stable.
Signal types
Clocks are separate type: |
1
, |
2
.
Two types of stable data signal:
stable |
1
(s |
1
)
stable |
2
(s |
2
)
A stable signal has a complementary
valid signal:
stable |
2
(s |
2
) = valid |
1
(v |
1
)
Stable data signal
inactive clock
stable until latch
feeding this
logic goes active
stable |
2
becomes
valid at end of |
1
How clocking types combine
Clocking types in the two-phase
machine
combinational
logic
D Q
combinational
logic
D Q
I
1
(s |
2
)
|
1
O
1
(s |
2
)
I
2
(s |
1
)
O
2
(s |
1
)
s |
1
s |
2
|
2
Clocking type propagation
Combinational logic does not change
type of signal.
Primary inputs must be compatible.
Latches change signals from one
clock type to another.
In strict system, never mix clocks
with data signals in combinational
logic.
Two-coloring
combinational
logic
D Q
combinational
logic
D Q
I
1
(s |
2
)
|
1
O
1
(s |
2
)
I
2
(s |
1
)
O
2
(s |
1
)
s |
1
s |
2
|
2
Example: shift register
Want to displace bit by n registers in
n cycles.
Each register requires two phases:
Shift register layout
Forms a linear array:
c1(latch)
|
1
|
1

c2(latch)
|
2
|
2

c3(latch)
|
1
|
1

c4(latch)
|
2
|
2

V
DD
V
SS
in
out
Shift register operation
|
1
= 1, |
2
= 0
|
1
= 0, |
2
= 1
Non-strict disciplines
Some relaxation of the rules can be
useful:
reduce area;
increase performance.
Rules must be relaxed in a way that
ensures the machine will still work.
Qualified clocks
Use logic to generate a clock signal
which is not always active.
Qualification must not introduce
glitches into the clockglitches
violate the fundamental definition of a
clock by introducing extra edges.
Use stable signals to qualify clocks.
Uses of qualified clocks
May want to conditionally load a
register.
May qualify a clock to turn off
machine for low-power operation.
Latch must be not lose its value
during inactive period.
Difficult to ensure that logic value will
come high in timeuse quasi-static
latch.
Recirculating latch
q|
1
|
2
s |
2
s |
2
s |
1
Qualified clocks and skew
Logic in the clocking path introduces
delay.
Delay can cause clock to arrive at
latches at different times, violating
clocking assumptions.
When designing qualification logic:
minimize and check skew;
sharpen clock edge.
Qualification skew example
Topics
Sequential machine implementation:
clocking.
Sequential machine design.
Clock period
For each phase, phase period must be
longer than sum of:
combinational delay;
latch propagation delay.
Phase period depends on longest
path.
Unbalanced delays
Logic with unbalanced delays leads to
inefficient use of logic:
long clock period short clock period
Retiming
Retiming moves memory elements
through combinational logic:
Retiming properties
Retiming changes encoding of values
in registers, but proper values can be
reconstructed with combinational
logic.
Retiming may increase number of
registers required.
Retiming must preserve number of
latches around a cyclemay not be
possible with reconvergent fanout.
Advanced performance analysis
Latch-based systems always have
some idle logic.
Can increase performance by blurring
phase boundaries. Results in cycle
time closer to average of phases.
Example with unbalanced
phases
One phase is much longer than the
other:
Spreading out a phase
Compute only part of long paths in one
phase:
Spreading out a phase, contd.
Use other phase for end of long logic
block and all of short logic block:
Problems
Hard to debugcant stop the
system.
Hard to initialize system state.
More sensitive to process variations.
Sequential machine design
Two ways to specify sequential
machine:
structure: interconnection of logic gates
and memory elements.
function: Boolean description of next-
state and output functions.
Best way depends on type of machine
being described.
Counter
Easy to specify as one-bit counter.
Harder to specify n-bit counter
behavior.
Can specify n-bit counter as structure
made of 1-bit counters.
One-bit counter
Truth table:

count C
in
next C
out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
One-bit counter implementation
One-bit counter operation
All operations are performed as s|
2
.
XOR computes next value of this bit
of counter.
NAND/inverter compute carry-out.
One-bit counter sticks
l1(latch) n(NAND) i(INV) x(XOR) l2(latch)
C
in
C
out
V
DD
V
SS
|
1
|
1
|
2
|
2

n-bit counter structure
State transition graphs/tables
Basic functional description of FSM.
Symbolic truth table for next-state,
output functions:
no structure of logic;
no encoding of states.
State transition graph and table are
functionally equivalent.
01 string recognizer
Behavior of machine which recognizes
01 in continuous stream of bits:

time 0 1 2 3 4 5
input 0 0 1 1 0 1
state bit1 bit2 bit2 bit1 bit1 bit2
next bit2 bit2 bit1 bit1 bit2 bit1
output 0 0 1 0 0 1
01 recognizer operation
Waits for 0 to appear in state bit1.
Goes into separate state bit2 when 0
appears.
If 1 appears immediately after 0,
cant have a 01 on next cycle, so can
go back to wait for 0 in state bit1.
State transition table
Symbolic state transition table:

input present next output
0 bit1 bit2 0
1 bit1 bit1 0
0 bit2 bit2 0
1 bit2 bit1 1
State transition graph
Equivalent to state transition table:
State assignment
Must find binary encoding for
symbolic statesstate assignment.
Choice of state assignment directly
affects both the next-state and
output logic:
area;
delay.
May also encode some machine
inputs/outputs.
01 recognizer encoding
Choose bit1= 0, bit2 = 1:

input present next output
0 0 1 0
1 0 0 0
0 1 1 0
1 1 0 1
Logic implementation
After encoding, truth table can be
implemented in gates:
Traffic light controller
Intersection of two roads:
highway (busy);
farm (not busy).
Want to give green light to highway
as much as possible.
Want to give green to farm when
needed.
Must always have at least one red
light.
Traffic light system
highway
farm road
sensor
traffic
light
System operation
Sensor on farm road indicates when
cars on farm road are waiting for
green light.
Must obey required lengths for green,
yellow lights.
Traffic light machine
Build controller out of two machines:
sequencer which sets colors of lights,
etc.
timer which is used to control durations
of lights.
Separate counter isolates logical
design from clock period.
Separate counter greatly reduces
number of states in sequencer.
Sequencer state transition
graph
hwy-
green
farm-
green
hwy-
yellow
farm-
yellow
(cars & long) / 0 green red
cars & long / 1 green red
short /
0 yellow red
short / 1 yellow red
short /
0 red yellow
short/ 1 red yellow
Topics
State assignment.
Power optimization of sequential
machines.
Design validation.
Sequential testing.
State assignment
Encoding bits in symbolic state =
state assignment.
State assignment affects:
combinational logic area;
combinational logic delay;
memory element area.
State assignment in n-space
0
s1 code = 111
s2 code = 110
1
1
1
State assignment and delay
output
Next state
Power optimization
Memory elements stop glitch
propagation:
Sequential testing
Much harder than combinational
testingcant set memory element
values directly.
Must apply sequences to put machine
in proper state for test, be able to
observe value of test.
Example
Testing the machine
To test NAND for stuck-at-1, must set
both NAND inputs to 1.
Primary input i1 can be controlled
directly.
To set lower NAND input, must set
state to ps0 = ps1 = 1.
Example state machine
State codes:
s0 = 11
s1 = 10
s2 = 01
s3 = 00
Controlling an FSM
Dont know initial state of machine.
Must find a sequence which drives
machine to required state
independent of initial state.
State sequence for test:
* -> s0 -> s1 -> s3.
Time-frame expansion
A model for sequential test: unroll
machine in time.
Time frame expansion illustrates how
single-stuck-at fault in sequential
machine appears to be multiple-SA
fault.
Time-frame expansion example
Unreachable states
State assignment may cause some
states to be unreachable.
As a result, it may not be possible to
apply some required test values.
Unreachable state example
s
0

s
1

s
2

1/
0/
1/
0/ 0/
1/
Example
State codes:
s0 = 00
s1 = 01
s2 = 10.
This creates a fourth state which is
unreachable.
Implemented FSM
00 01
10 11
1/ 0/
1/
0/ 0,1/
0/
1/
LSSD
LSSD = level-sensitive scan design.
Way to achieve full controllability,
observability of registers.
Links all registers in a scan chain.
LSSD latch
Partial scan
Full scan is expensivemust roll out
and roll in state many times during a
set of tests.
Partial scan selects some registers for
scanability.
Requires analysis to choose which
registers are best for scan.
UNIT::4::Topics
Shifters.
Adders and ALUs.
Combinational shifters
Useful for arithmetic operations, bit
field extraction, etc.
Latch-based shift register can shift
only one bit per clock cycle.
A multiple-shift shifter requires
additional connectivity.
Barrel shifter
Can perform n-bit shifts in a single
cycle.
Efficient layout.
Does require transmission gates and
long wires.
Barrel shifter structure
Accepts 2n data inputs and n control
signals, producing n data outputs.
d
a
t
a

1

d
a
t
a

2

n bits
n bits
o
u
t
p
u
t

n bits
Barrel shifter operation
Selects arbitrary contiguous n bits out
of 2n input bits.
Examples:
right shift: data into top, 0 into bottom;
left shift: 0 into top, data into bottom;
rotate: data into top and bottom.
Barrel shifter layout
Two-dimensional array of 2n vertical
X n horizontal cells.
Input data travels diagonally upward.
Output wires travel horizontally.
Control signals run vertically. Exactly
one control signal is set to 1, turning
on all transmission gates in that
column.
Barrel shifter cell
Barrel shifter in action
Analysis
Large number of cells, but each one is
small.
Delay is large, considering long wires
and transmission gates.
Adders
Adder delay is dominated by carry
chain.
Carry chain analysis must consider
transistor, wiring delay.
Modern VLSI favors adder designs
which have compact carry chains.
Full adder
Computes one-bit sum, carry:
s
i
= a
i
XOR b
i
XOR c
i

c
i+1
= a
i
b
i
+ a
i
c
i
+ b
i
c
i
Ripple-carry adder: n-bit adder
built from full adders.
Delay of ripple-carry adder goes
through all carry bits.
Carry-lookahead adder
First compute carry propagate,
generate:
P
i
= a
i
+ b
i

G
i
= a
i
b
i

Compute sum and carry from P and
G:
s
i
= c
i
XOR P
i
XOR G
i

c
i+1
= G
i
+ P
i
c
i
Carry-lookahead expansion
Can recursively expand carry
formula:
c
i+1
= G
i
+ P
i
(G
i-1
+ P
i-1
c
i-1
)
c
i+1
= G
i
+ P
i
G
i-1
+ P
i
P
i-1
(G
i-2
+ P
i-1
c
i-2
)
Expanded formula does not depend
on intermerdiate carries.
Allows carry for each bit to be
computed independently.
Depth-4 carry-lookahead
Analysis
Deepest carry expansion requires
gates with large fanin: large, slow.
Carry-lookahead unit requires
complex wiring between adders and
lookahead unitvalues must be
routed back from lookahead unit to
adder.
Layout is even more complex with
multiple levels of lookahead.
Carry-skip adder
Looks for cases in which carry out of
a set of bits is identical to carry in.
Typically organized into m-bit stages.
If a
i
= b
i
for every bit in stage, then
bypass gate sends stages carry input
directly to carry output.
Two-bit carry-skip structure
Carry-select adder
Computes two results in parallel, each
for different carry input assumptions.
Uses actual carry in to select correct
result.
Reduces delay to multiplexer.
Carry-select structure
Manchester carry chain
Precharged carry chain which uses P
and G signals.
Propagate signal connects adjacent
carry bits.
Generate signal discharges carry bit.
Worst-case discharge path goes
through entire carry chain.
Manchester carry chain circuit
Serial adder
May be used in signal-processing
arithmetic where fast computation is
important but latency is unimportant.
Data format (LSB first):
0 1 1 0
LSB
Serial adder structure
LSB control signal clears the carry shift
register:
ALUs
ALU computes a variety of logical and
arithmetic functions based on
opcode.
May offer complete set of functions of
two variables or a subset.
ALU built around adder, since carry
chain determines delay.
Function block circuit
Function blocks and ALUs
Function block may be used to
compute required intermediate
signals for a full-function ALU.
Requires little area.
Transmission gates may introduce
significant delay.
ALU structure
ALU design
P and G compute intermediate values
from inputs. May not correspond to
carry lookahead P and G for non-
addition functions.
Add unit is adder of choice.
Output unit computes from sum,
propagate signal.
Topics
Multipliers.
Elementary school algorithm
0 1 1 0 multiplicand
x 1 0 0 1 multiplier
0 1 1 0
+ 0 0 0 0
0 0 1 1 0
+ 0 0 0 0
0 0 0 1 1 0
+ 0 1 1 0
0 1 1 0 1 1 0
partial product
Word serial multiplier
Combinational multiplier
Uses n adders, eliminates registers:
Array multiplier
Array multiplier is an efficient layout
of a combinational multiplier.
Array multipliers may be pipelined to
decrease clock period at the expense
of latency.
Array multiplier organization
0 1 1 0
x 1 0 0 1
0 1 1 0
+ 0 0 0 0
0 0 1 1 0
+ 0 0 0 0
0 0 0 1 1 0
+ 0 1 1 0
0 1 1 0 1 1 0
product
skew array
for rectangular
layout
multiplicand
multiplier
Unsigned array multiplier
+
x0y0 x1y0 x2y0
xny0
0
x0y1
+
x1y1
0
+
x0y2
+
x1y2
+
0
+
P(2n-1)
P(2n-2)
P0
Baugh-Wooley multiplier
Algorithm for twos-complement
multiplication.
Adjusts partial products to maximize
regularity of multiplication array.
Moves partial products with negative
signs to the last steps; also adds
negation of partial products rather
than subtracts.
Booth multiplier
Encoding scheme to reduce number
of stages in multiplication.
Performs two bits of multiplication at
oncerequires half the stages.
Each stage is slightly more complex
than simple multiplier, but
adder/subtracter is almost as
small/fast as adder.
Booth encoding
Twos-complement form of multiplier:
y = -2
n
y
n
+ 2
n-1
y
n-2
+ 2
n-2
y
n-2
+ ...
Rewrite using 2
a
= 2
a+1
- 2
a
:
y = -2
n
(y
n-1
-y
n
) + 2
n-1
(y
n-2
-y
n-1
) + 2
n-
2
(y
n-3
-y
n-2
) + ...
Consider first two terms: by looking
at three bits of y, we can determine
whether to add x, 2x to partial
product.
Booth actions
y
i
y
i-1
y
i-2
increment
0 0 0 0
0 0 1 x
0 1 0 x
0 1 1 2x
1 0 0 -2x
1 0 1 -x
1 1 0 -x
1 1 1 0
Booth example
x = 011001 (25
10
), y = 101110 (-
18
10
).
y
1
y
0
y
-1
= 100, P
1
= P
0
- (10 011001)
= 11111001110.
y
3
y
2
y
1
= 111, P
2
= P
1
+ 0 =
11111001110.
y
5
y
4
y
3
= 101, P
3
= P
2
- 0110010000 =
11000111110.
Booth structure
Wallace tree
Reduces depth of adder chain.
Built from carry-save adders:
three inputs a, b, c
produces two outputs y, z such that y +
z = a + b + c
Carry-save equations:
y
i
= parity(a
i
,b
i
,c
i
)
z
i
= majority(a
i
,b
i
,c
i
)
Wallace tree structure
Wallace tree operation
At each stage, i numbers are
combined to form ceil(2i/3) sums.
Final adder completes the
summation.
Wiring is more complex.
Can build a Booth-encoded Wallace
tree multiplier.
Serial-parallel multiplier
Used in serial-arithmetic operations.
Multiplicand can be held in place by
register.
Multiplier is shfited into array.
Serial-parallel multiplier
structure
Topics
Memories:
ROM;
SRAM;
DRAM.
Datapaths.
PLAs.
High-density memory
architecture
Memory operation
Address is divided into row, column.
Row may contain full word or more than
one word.
Selected row drives/senses bit lines in
columns.
Amplifiers/drivers read/write bit lines.
Read-only memory (ROM)
ROM core is organized as NOR
gatespulldown transistors of NOR
determine programming.
Erasable ROMs require special
processing that is not typically
available.
ROMs on digital ICs are generally
mask-programmedplacement of
pulldowns determines ROM contents.
ROM core circuit
Static RAM (SRAM)
Core cell uses six-transistor circuit to
store value.
Value is stored symmetricallyboth
true and complement are stored on
cross-coupled transistors.
SRAM retains value as long as power
is applied to circuit.
SRAM core cell
SRAM core operation
Read:
precharge bit and bit high;
set select line high from row decoder;
one bit line will be pulled down.
Write:
set bit/bit to desired (complementary)
values;
set select line high;
drive on bit lines will flip state if
necessary.
SRAM sense amp
Sense amp operation
Differential pairtakes advantage of
complementarity of bit lines.
When one bit line goes low, that arm
of diff pair reduces its current,
causing compensating increase in
current in other arm.
Sense amp can be cross-coupled to
increase speed.
3-transistor dynamic RAM
(DRAM)
First form of DRAMmodern
commercial DRAMs use one-transistor
cell.
3-transistor cell can easily be made
with a digital process.
Dynamic RAM loses value due to
charge leakagemust be refreshed.
3-T DRAM core cell
3-T DRAM operation
Value is stored on gate capacitance of
t
1
.
Read:
read = 1, write = 0, read_data is
precharged;
t
1
will pull down read_data if 1 is stored.
Write:
read = 0, write = 1, write_data = value;
guard transistor writes value onto gate
capacitance.
Data paths
A data path is a logical and a physical
structure:
bitwise logical organization;
bitwise physical design.
Datapath often has ALU, registers,
some other function units.
Data is generally passed via busses.
Typical data path structure
Slice includes one bit of function units,
connected by busses:
registers shift ALU
bus
Bit-slice structure
Many arithmetic and logical functions
can be defined recursively on bits of
word.
A bit-slice is a one-bit (or n-bit)
segment of an operation of minimum
size to ensure regularity.
Regular logical structure allows
regular physical structure.
Abutting and pitch-matching
Cells in bit-slice may be abutted
togetherrequires matching positions
on terminals.
Pitch-matching is designing cells to
ensure that pins are at proper
positions for abutting.
Wiring plans
A wiring plan shows layer
assignments and directions for major
signals.
Put most important signals on lowest-
impedance, accessible layers.
cell1 cell2 cell3
V
DD
V
SS
Bus circuits
Cannot support full connectivity
between all data path elements
must choose number of transfers per
cycle allowed.
A bus circuit is a specialized
multiplexer circuit.
Two major choices: pseudo-nMOS,
precharged.
Pseudo-nMOS bus circuit
Precharged bus circuit
Programmable logic array (PLA)
Used to implement specialized logic
functions.
A PLA decodes only some addresses
(input values); a ROM decodes all
addresses.
PLA not as common in CMOS as in
nMOS, but is used for some logic
functions.
PLA organization
AND plane OR plane
p1
p2
p3
p4
f
0
f
1
i
0
i
0
i
1
i
1

product term
PLA structure
AND plane, OR plane, inverters
together form complete two-level
logic functions.
Both AND and OR planes are
implemented as NOR circuits.
Pulldown transistors form
programming/personality of PLA.
Transistors may be referred to as
programming tabs.
PLA AND/OR cell
programming
tab
no tab
V
SS
input 1 input 2
output 1
output 2
UNIT:5::Topics
Block placement.
Global routing.
Switchbox routing.
Floorplanning strategies
Floorplanning must take into account
blocks of varying function, size,
shape.
Must design:
space allocation;
signal routing;
power supply routing;
clock distribution.
data path
RAM
std cell
Bricks-and-mortar floorplan
blocks
Purposes of floorplanning
Early in design:
Prepare a floorplan to budget area, wire
area/delay. Tradeoffs between blocks
can be negotiated.
Late in design:
Make sure the pieces fit together as
planned.
Implement the global layout.
Types of routing
Channel routing:
channel may grow in one dimension to
accommodate wires;
pins generally on only two sides.
Switchbox routing:
cannot grow in any dimension;
pins are on all four sides, fixing
dimensions of the box.
Channels and switchboxes
channel switchbox
channel
switchbox
pins
Block placement
Blocks have:
area;
aspect ratio.
Blocks may be placed at different
rotations and reflections.
Uniform size blocks are easier to
interchange.
Blocks and wiring
Cannot ignore wiring during block
placementlarge wiring areas may
force rearrangement of blocks.
Wiring plan must consider area and
delay of critical signals.
Blocks divide wiring area into routing
channels.
Channel definition
Channels end at block boundaries.
Several alternate channel definitions
are possible:
A
B C
channel 1
ch 2
ch 1 ch 2
ch 3
Channel definition changes with
block spacing
Changing spacing changes relationship
between block edges:
A
B
C C
Channel graph
A
B
C
D
E
Channel graph usage
Nodes are channels, edges placed
between two channels that touch.
Channel graph shows paths between
channels.
Channel graph can be used to guide
global routing.
Channels must be routed in
order
Wire out of end of one channel creates
pin on side of next channel:
channel A
channel B
constraint
Windmills
Can create an unroutable combination
of channels with circular constraints:
A
B
C
D
Slicable floorplan
Slicability property
A slicable floorplan can be recursively
cut in two without cutting any blocks.
A slicable floorplan is guaranteed to
have no windmills, therefore
guaranteed to have a feasible order
of routing for the channels.
Slicability is a desirable property for
floorplans.
Global routing
Goal: assign wires to paths through
channels.
Dont worry about exact routing of
wires within channel.
Can estimate channel height from
global routing using congestion.
Line probe routing
Heuristic method for finding a short
route.
Works with arbitrary combination of
obstacles.
Does not explore all possible paths
not optimal.
Line probe example
A
A
line 1
line 2
Channel utilization
Want to keep all channels about
equally full to minimize wasted area.
Important to route time-critical
signals first.
Shortest path may not be best for
global wiring.
In general, may need to rip-up wires
and reroute to improve the global
routing.
Switchbox routing
Cant expand a switchbox to make
room for more wiring.
Switchbox may be defined by
intersection of channels.
Routing order and switchboxes
Switchboxes frequently need more
experimentation with wiring order
because nets may block other nets:
B
A
B
A
B blocks A
Topics
Power/ground routing.
Clock routing.
Floorplanning tips.
Off-chip connections.
Power distribution
Must size wires to be able to handle
currentrequires designing topology
of V
DD
/V
SS
networks.
Want to keep power network in
metalrequires designing planar
wiring.
Low-resistance jumper
We want to avoid this:
Interdigitated power and
ground lines
V
DD
V
SS
Power tree design
Each branch must be able to supply
required current to all of its
subsidiary branches:
I
x
= E
b c x
I
b

Trees are interdigitated to supply
both sides of power supply.
Planar power/ground routing
theorem
Draw a dividing line through each cell
such that all V
DD
terminals are on one
side and all V
SS
terminals on the
other.
If floorplan places all cells with V
DD
on same
side, there exists a routing for both V
DD
and
V
SS
which does not require them to cross.
cell
V
DD
V
DD
V
SS
V
SS
Planar routing theorem
example
A
B
C
V
DD

V
SS

V
DD

V
DD

V
DD

V
DD

V
SS

V
SS

V
SS

V
SS

cut line
cut line
no cut line
no connection
Power supply noise
Variations in power supply voltage
manifest themselves as noise into the
logic gates.
Power supply wiring resistance
creates voltage variations with
current surges.
Voltage drops on power lines depend
on dynamic behavior of circuit.
Tackling power supply noise
Must measure current required by
each block at varying times.
May need to redesign power/ground
network to reduce resistance at high
current loads.
Worst case, may have to move some
activity to another clock cycle to
reduce peak current.
Clock distribution
Goals:
deliver clock to all memory elements
with acceptable skew;
deliver clock edges with acceptable
sharpness.
Clocking network design is one of the
greatest challenges in the design of a
large chip.
Clock delay varies with position
H-tree
|
Clock distribution tree
Clocks are generally distributed via
wiring trees.
Want to use low-resistance
interconnect to minimize delay.
Use multiple drivers to distribute
driver requirementsuse optimal
sizing principles to design buffers.
Clock lines can create significant
crosstalk.
Clock distribution tree example
Floorplanning tips
Develop a wiring plan. Think about
how layers will be used to distribute
important wires.
Sweep small components into larger
blocks. A floorplan with a single NAND
gate in the middle will be hard to
work with.
Design wiring that looks simple. If it
looks complicated, it is complicated.
Floorplanning tips, contd.
Design planar wiring. Planarity is the
essence of simplicity. It isnt always
possible, but do it where feasible (and
where it doesnt introduce
unacceptable delay).
Draw separate wiring plans for power
and clocking. These are important
design tasks which should be tackled
early.
Off-chip connections
A package holds the chip. Packages
can introduce significant inductance.
Pads on the chip allow the wires on
chip to be connected to the package.
Pads are library components which
require careful electrical design.
Structure of a typical package
Package structure
Package body is physical/thermal
support for chip.
Cavity holds chip.
Leads in package connect to pads,
provide substrate connection to chip.
Some packages
DIP
PGA
PLCC
Pin inductance
Package pins have non-trivial
inductance.
Power and ground nets typically
require many pins to supply required
current through the packaging
inductance.
Pin inductance example
Power circuit including pin indutance:
Pin inductance example, contd
Voltage across pin inductance:
v
L
= L di
L
/ dt
Current surge into chip causes
inductive voltage drop:
L = 0.5 nH;
i
L
= 1A;
v
L
= 0.5 V.
I/O architecture
Pads are placed on top-layer metal to
provide a place to bond to the
package.
Pads are typically placed around
periphery of chip.
Some advanced packaging systems
bond directly to package without
bonding wire; some allow pads across
entire chip surface.
Pad frame architecture
Pad frame design
Must supply power/ground to each
pad as well as chip core.
Positions of pads around frame may
be determined by pinout
requirements on package.
Want to distribute power/ground pins
as evenly as possible to minimize
power distribution problems.
Input pads
Main purpose is to provide
electrostatic discharge (ESD)
protection.
Gate voltage of transistor is very
sensitivecan be permanently
damaged by high voltage.
Static electricity in room is sufficient
to damage CMOS ICs.
Input pad circuits
Resistor is used in series with pad to
limit current caused by voltage spike.
May use parasitic bipolar transistors
to drain away high voltages:
one for positive pulses;
another for negative pulses.
Must design layout to avoid latch-up.
Output pad circuits
Dont need ESD protectiontransistor
gates not connected to pad.
Must be able to drive capacitive load
of pad + outside world.
May need voltage level shifting, etc.
to be compatible with other logic
families.
Output pad circuit, contd.
Three-state pad
Combination input/output, controlled
by mode input on chip.
Pad includes logic to disconnect
output driver when pad is used as
input.
Must be protected against ESD.
Three-state pad circuit
Boundary scan
Boundary scan is a technique for
testing chips on boards. Pads on
chips are arranged into a scan chain
that can be used to observe and
control pins of all chips.
Requires some control circuitry on
pads along with an on-chip controller
and boundary-scan-mode control
pins.
UNIT:6::Topics
Basics of register-transfer design:
data paths and controllers;
ASM charts.
Register-transfer design
A register-transfer system is a
sequential machine.
Register-transfer design is
structuralcomplex combinations of
state machines may not be easily
described solely by a large state
transition graph.
Register-transfer design concentrates on
functionality, not details of logic design.
Register-transfer system
example
A register-transfer machine has
combinational logic connecting
registers:
D Q
combinational
logic
D Q D Q
combinational
logic
combinational
logic
Block diagrams
Block diagrams specify structure:
wire bundle
of width 5
Register-transfer simulation
Simulates to clock-cycle accuracy.
Doesnt guarantee timing.
Important to get proper function of
machine before jumping into detailed
logic design. (But be sure to take into
account critical delays when choosing
register-transfer organization.)
Simulation coding
Hardware description languages are
typically supported by a simulation
system: VHDL, Verilog, etc.
Simulation engine takes care of
scheduling events during simulation.
Can hand-code a simulation in a
programming language.
Must be sure that register-transfer
events happen in proper order.
Sample VHDL code
sync: process begin
wait until CLOCKevent and CLOCK=1;
state <= state_next;
end process sync;
combin: process begin
case state is
when S0 =>
out1 <= a + c;
state_next <= S1;
...
end process combin;
sync process models
registers
combin process models
combinational logic
Sample C simulator
while (TRUE) {
switch (state) {
case S0:
x = a + b;
state = S1;
next;
case S1:
...
}
}

loop executed once
per clock cycle
each case corresponds
to a state; sets outputs,
next state
Data path-controller systems
One good way to structure a system
is as a data path and a controller:
data path executes regular operations
(arithmetic, etc.), holds registers with
data-oriented state;
controller evaluates irregular functions,
sets control signals for data path.
Data and control are equivalent
We can rewrite control into data and
visa versa:
control: if i1 = 0 then o1 <= a; else o1 <= b;
end if;
data: o1 <= ((i1 = 0) and a) or ((i1 = 1) and
b);
Data/control distinction is useful but
not fundamental.
Data operators
Arithmetic operations are easy to
spot in hardware description
languages:
x <= a + b;
Multiplexers are implied by
conditionals. Must evaluate entire
program to determine which sources
of data for registers.
Multiplexers also come from sharing
adders, etc.
Conditionals and multiplexers
if x = 0 then
reg1 <= a;
else
reg1 <= b;
end if;
code
register-transfer
Alternate data path-controller
systems
controller
data path
one controller,
one data path
controller
data path
controller
data path
two communicating
data path-controller
systems
ASM charts
An ASM chart is a register-transfer
description.
ASM charts let us describe function
without choosing a partitioning
between control and data.
Once we have specified the function,
we can refine it into a block diagram
which partitions data and control.
Sample ASM chart
ASM state
An ASM state specifies a machine
state and a set of actions in that
state. All actions occur in parallel.
s1
x = a + b
y = c - d + e
o1 = 1
name of state (notation only)
Actions in state
Actions in a state are unconditionally
executed.
A state can execute as many actions
as you want, but you must eventually
supply hardware for all those actions.
A register may be assigned to only
once in a state (single-assignment
rule).
Implementing operations in an
ASM state
state with one addition
two additions requires two adders
Sequences of states
States are linked by transitions.
States are executed sequentially.
Each state may take independent
actions (including assigning to a
variable assigned to in a previous
state).
s1
x = a + b
s2
x = c + d
y = a + d
Data paths from states
Maximum amount of hardware in data
path is determined by state which
executes the most functionality.
Function units implementing data
operations may be reused across
states, but multiplexers will be
required to route values to the shared
function units.
Function unit sharing example
mux allows +
to compute
a+b, a+c
Conditionals
Conditional chooses which state to
execute next based on primary input
or present state value.
Can be drawn in either of two ways:
a = b x
00 01 10 11
T
F
Execution of conditionals
An ASM chart describes a Moore
sequential machine. If the logic
associated with an ASM chart
fragment doesnt correspond to a
legal sequential machine, then it isnt
a legal ASM chart.
Conditional can evaluate only present
state or primary input value on
present cycle.
Implementing an ASM branch in
a Moore machine
ASM chart
state transition
graph of
controller
Mealy machines and ASM
Mealy machine requires a conditional
output.
ASM notation for conditional output:
i1
0
y = c + d
Extracting data path and
controller
ASM chart notation helps identify
data, control.
Once you choose what values and
operations go into the data path, you
can determine by elimination what
goes into the controller.
Structure of the ASM chart gives
structure of controller state transition
graph.
Data path-controller extraction
Topics
Modeling with hardware description
languages (HDLs).
Hardware description languages
Textual languages for describing
hardware:
structure;
function.
Most people today use textual
languages rather than schematics for
most digital design.
Schematics make poor use of screen
space.
Major HDLs
Two major HDLs designed for
simulation:
VHDL;
Verilog.
Similar capabilities but somewhat
different language philosophies.
EDIF is a standard netlist format.
Simulation vs. programming
Simulation tags computations with
times.
Must know when signals change to
properly simulate hardware.
Simulation is parallel.
Many statements can execute at the
same (simulation) time.
Just like hardware.

Types of simulation
Compiled code simulation.
Generate program that evaluates a
hardware block.
Operational details within the hardware
block are lost.
Event-driven simulation.
Propagate events through simulation.
Dont simulate a block until its inputs
change.
Event-driven simulation
An event is a
change in a nets
value.
An event has two
components:
value;
time.

time t=35 ns
net1=0 @ 35 ns
net
event
n
e
t
1

Propagate events
only when nets
change value.
If an input change
doesnt cause an
output change, no
event is
propagated.
0
1
1
0
no
event
1
0
Timewheel
The timewheel is a data structure in
the simulator that efficiently
determines the order of events
processed.
Events are placed on the timewheel in
time order.
Events are taken out of the head of
the timewheel to process them in
order.
Timewheel operation
a
b
c
1
0
1
a=1 @ 0 ns
netlist
timewheel
b=1 @ 1 ns
1
c=0 @ 2 ns
0
time
Order of evaluation
Order of evaluation is important.
Causality must be obeyed.
Evaluating events in the wrong order
can cause inaccurate results.
Order of evaluation example
a
b
c
0
0
0
netlist
timewheel
b=1 @ 1 ns
1
d=1 @ 2 ns
1
d
e
1
e=0 @ 4 ns
0
1
time
Modeling
Structural modeling describes the
connections between components.
Netlists are structural models.
Behavioral models describes the
functional relationship between inputs
and outputs.
Similar to programming but values are
events.
HDLs language constructs
Must be able to define component types.
A model may be behavioral or structural.
May be able to define abstract data types.
A wire may carry an enumerated value.
Multi-valued simulation may be defined using
abstract data types.
May be able to define modules to control
the scope of names.
Testbenches
A testbench is a model used to
exercise a simulation.
Provides stimulus.
Checks outputs.
Testbenches help automate design
verification.
Rerun edited module against testbench.
Run models at behavioral, RTL levels
against the same testbench.
Synthesis subsets
VHDL and Verilog were designed for
simulation.
A synthesis subset is:
synthesizable;
produces consistent simulation results.
Different tools may use different
synthesis subsets.
Register-transfer synthesis
Most common type of synthesis.
Synthesizes gates from abstract RT
model.
Registers are explicit.
Some tools will infer storage elements---
be careful.
Optimized for performance, area,
power.
Topics
VHDL register-transfer modeling:
basics using traffic light controller;
synthesis.
VHDL
Combines a general-purpose
programming language and an HDL.
Modeled on Ada programming language.
VHDL is a rich language:
modules;
abstract data types.
VHDL is case-insensitive.
Abstract data types
package lights is
---this is a comment
subtype light is bit_vector(0 to 1);
constant red : light : B00;
constant green : light : B01;
constant yellow : light : B10;
end lights;
VHDL entities
An entity defines the interface to the
module.
May plug various descriptions into the
entity interface:
behavioral;
RT;
gate.
VHDL constants
Bit constant:
0, 1
Bit vector constant:
B0101
Traffic light entity declaration
entity tlc_fsm is
port( CLOCK: in BIT; -- machine clock
reset : in BIT; -- global reset
cars : in BIT; -- car signal
short, long : in BIT;
highway_light : out light := green;
farm_light : out light := red;
start_timer : out BIT
);
VHDL processes
A process is a unit of parallel execution.
All processes in an entity execute in parallel.
Processes are used to build up behavior.
Our RT model will have at least two
processes:
combinational process for the logic;
sequential process for the flip-flops.
VHDL process example
combin : process(state,hg)
begin
highway_light <= green;
end process combin;
Sensitivity list
Event assignment
VHDL formulas
a and b Boolean AND
a or b Boolean OR
not a Boolean NOT
a <= b Signal assignment
a = b Equality
after 5 ns time

VHDL data types
std_logic Binary signal
std_logic_vector Binary signal vector

Operations in the process
if (b or c) = 1 then
y <= 1;
else
y <= 0;
y <= 1;
else
z <= a or b;
y assigned value
in both cases
different net assigned
in true, false cases
Conditional assignments
y <= 1;
else
z <= a or b;
Simulation:
Condition is tested
based on current
signal states.
Only one net gets
an event.
Synthesis:
Creates dont-cares
for y and z.
Some useful constructs
avec: out std_logic_vector(11 downto 0)
vector
constant zerovec: std_logic_vector(0 to 7) :=
B00000000;
constant vector
sum <= a + b;
adder
Structure of a VHDL model
Library use statements.
Entity declaration.
Architecture declaration.
Processes, etc. that form the
architecture.
An entity may have multiple
instantiations.
A synthesizable VHDL
archtiecture
Declarations of types and signals.
Combinational process.
May be several combinational processes
that communicate via signals.
Synchronous process.
A synthesizable synchronous
process
sync: process(CLOCK)
begin
wait until CLOCKevent and CLOCK =
1;
ctrl_state <= ctrl_next;
end process sync;
Transfers next state to present state
Ensures evaluation on clock edge
Testbench structure
Unit under test
(UUT)
testbench
tester
VHDL testbed organization
Library calls.
Entity declaration.
Generally has no inputs or outputs.
Architecture section.
UUT is a component.
Testbench logic is a process.
Testbench tester process
tester: process
begin
reset <= 1;
clock <= 0;
wait for 5 ns;
clock <= 1;
wait for 5 ns;
assert(highway_light = green);
Clock tick
Checks output of UUT
Topics
Verilog register-transfer modeling:
basics using traffic light controller;
synthesis.
Verilog
Verilog was designed as an efficient
simulation language.
Relatively simple, terse syntax.
Most popular HDL in use today.
Verilog formulas
a & b Boolean AND
a | b Boolean OR
~a Boolean NOT
a = b Assignment
a == b Equality
#1 time
a <= b Concurrent
assignment

Verilog constants
Bit constant:
0, 1
Bit vector constant:
4b1010
Some useful constructs
define aconst 2b00
constant vector
$monitor($time,,a=%b, b=%b,a,b);
value monitor output
#1 a=0; b=0
#2 a=1; b=0
sequence of waveforms
Four-valued OR function
0 1 X z
0 0 1 x x
1 1 1 1 1
X x 1 x x
Z x 1 x x

Four-valued AND function
0 1 X z
0 0 0 x x
1 0 1 x x
X x x x x
Z x x x x

Verilog structural model
Module adder(a,b,cin,sum,cout);
input a, b, cin;
output sum, cout;
xor #2 s(sum,a,b,cin); // sum
and #1 // carry out
c1(x1,a,b); c2(x2,a,cin); c3(x3,b,cin);
or #1
c4(cout,x1,x2,x3);
endmodule
Time delay for output
Output
wire
Input wires
If statements
if (b | c) then
y = 1;
else
y <= 0;
if (b | c) then
y = 1;
else
z = a | b;
y assigned value
in both cases
different net assigned
in true, false cases
Conditional assignments
if (b | c) then
y = 1;
else
z = a | b;
Simulation:
Condition is tested
based on current
signal states.
Only one net gets
an event.
Synthesis:
Creates dont-cares
for y and z.
Loop statement
A loop performs an operation over an
array of signals:
for (i=0; i<N; i=i+1)
x[i] = a[i] & b[i];
always statement
always guards execution of a block of
statements.
Block is always executed on the logical
condition.
always @(sigval) begin .. end
Structure of a Verilog model
Module statement.
Declares I/O pin names.
Declarations:
inputs and outputs;
registers.
Body.
A synthesizable Verilog
archtiecture
Declarations of pins and registers.
Definitions of constants (similar to C
#define statement).
define GREEN 2b11
Combinational and sequential
portions.
Within @always statements.
Verilog combinational portion
always @(ctrl_state or short or long or cars)
begin
when HG: begin // state hwy-green
highway_light = GREEN;
farm_light = RED;
if (cars & long) then
begin ctrl_next = HY; start_timer = 1; end
else begin ctrl_next - HG; start_timer = 0;
end
end
Verilog sequential portion
always @(posedge clock or negedge reset)
if (~reset)
ctrl_state <= 0;
else
ctrl_state <= ctrl_next;
end
Condition on clock/reset
Transfer of next state
to current state
Testbench structure
Unit under test
(UUT)
testbench
tester
Verilog testbed organization
Module declaration.
Two components: UUT and tester.
Definition of UUT.
Definition of tester.
Testbench tester process
initial
begin
$monitor($time,,a=%b,a);
#1 a=0; b=0; cin=0;
#1 a=1; b=0; cin=0;
#2 a=1; b=1; cin=1;
end
endmodule
Test inputs
Prints signal values
Topics
High-level synthesis.
Architectures for low power.
Testability and architecture.
High-level synthesis
Sequential operation is not the most
abstract description of behavior.
We can describe behavior without
assigning operations to particular
clock cycles.
High-level synthesis (behavioral
synthesis) transforms an unscheduled
behavior into a register-transfer
behavior.
Tasks in high-level synthesis
Scheduling: determines clock cycle on
which each operation will occur.
Binding (allocation): chooses which
function units will execute which
operations.
Functional modeling code in
VHDL
o1 <= i1 or i2;
if i3 = 0 then
o1 <= 1;
o2 <= a + b;
else
o1 <= 0;
end if;
clock cycle boundary can
be moved to design different
register transfers
Data dependencies
Data dependencies describe
relationships between operations:
x <= a + b; value of x depends on a, b
High-level synthesis must preserve
data dependencies.
Data flow graph
Data flow graph (DFG) models data
dependencies.
Does not require that operations be
performed in a particular order.
Models operations in a basic block of
a functional modelno conditionals.
Requires single-assignment form.
Data flow graph construction
original code:
x <= a + b;
y <= a * c;
z <= x + d;
x <= y - d;
x <= x + c;
single-assignment
form:
x1 <= a + b;
y <= a * c;
z <= x1 + d;
x2 <= y - d;
x3 <= x2 + c;
Data flow graph construction,
contd
Data flow forms directed acyclic graph
(DAG):
Goals of scheduling and
allocation
Preserve behaviorat end of
execution, should have received all
outputs, be in proper state (ignoring
exact times of events).
Utilize hardware efficiently.
Obtain acceptable performance.
Data flow to data path-
controller
One feasible schedule for last DFG:
Binding values to registers
registers fall on
clock cycle
boundaries
Choosing function units
muxes allow
function units
to be shared
for several
operations
Building the sequencer
sequencer requires three states,
even with no conditionals
Choices during high-level
synthesis
Scheduling determines number of
clock cycles required; binding
determines area, cycle time.
Area tradeoffs must consider shared
function units vs. multiplexers,
control.
Delay tradeoffs must consider cycle
time vs. number of cycles.
Finding schedules
Two simple schedules:
As-soon-as-possible (ASAP) schedule
puts every operation as early in time as
possible.
As-late-as-possible (ALAP) schedule puts
every operation as late in schedule as
possible.
Many schedules exist between ALAP
and ASAP extremes.
ASAP and ALAP schedules
ASAP
ALAP
Critical path of schedule
Longest path through data flow
determines minimum schedule
length:
Operator chaining
May execute several
operations in sequence in
one cycleoperator
chaining.
Delay through function
units may not be additive,
such as through several
adders.
Control implementation
Clock cycles are also known as
control steps.
Longer schedule means more states
in controller.
Cost of controller may be hard to
judge from casual inspection of state
transition graph.
Controllers and scheduling
functional
model:
x <= a + b;
y <= c + d;
one state
two states
Distributed control
one centralized controller
two distributed controllers
Synchronized communication
between FSMs
To pass values between two machines, must schedule output
of one machine to coincide with input expected by the other:
Hardwired vs. microcoded
control
Hardwired control has a state register
and random logic.
A microcoded machine has a state
register which points into a microcode
memory.
Styles are equivalent; choice depends
on implementation considerations.
Data path-controller delay
Watch out for long delay paths created
by combination of data path and
controller:
Architectures for low power
Two important methods:
architecture-driven voltage scaling
power-down modes
Architecture-driven voltage
scaling
Add extra logic to increase parallelism
so that system can run at lower rate.
Power improvement for n parallel
units over Vref:
P
n
(n) = [1 + C
i
(n)/nC
ref
+
C
x
(n)/C
ref
](V/V
ref
)
Power-down modes
CMOS doesnt consume power when
not transitioning. Many systems can
incorporate power-down modes:
condition the clock on power-down
mode;
add state to control for power-down
mode;
modify the control logic to ensure that
power-down/power-up dont corrupt
control state.
Architecture testing
Want to make system as testable as
possible with minimum cost in
hardware, testing time.
Can use knowledge of architecture to
help choose testability points.
May want to modify architecture to
improve testability.
Some scan latches are more
useful than others
Acyclic register-transfer graphs are
easy to test.
Register-transfers with feedback are
harder to teststate becomes
contaminated during test.
When choosing partial scan registers,
choose feedback paths first.
Identifying partial scan
opportunities
Construct register graph, which
shows connections between registers:
nodes are registers;
edge between two nodes if there is a
combinational path between them.
Sequential depth is distance from
primary input to a node.
Register graph example
machine
register graph
Analyzing register graphs
High sequential depth implies that the
register is harder to test.
Registers contained register-graph
cycles (FF2-FF3) are hard to test
(although self-loops are not hard).
Add partial scan registers to
effectively reduce sequential depth of
node and its neighbors.
Built-in self test (BIST)
Includes on-chip machine responsible
for:
generating tests;
evaluating correctness of tests.
Allows many tests to be applied.
Cant afford large memory for test
resultsrely on compression and
statistical analysis.
Generating vectors
Use a linear-feedback shift register to
generate a pseudo-random sequence
of bit vectors:
BIST architecutre
One LFSR to generates test sequence.
Another LFSR captures/compresses
results.
Can store a small number of signatures
which contain expected compressed
result for valid system.
UNIT:7::Topics
Design methodologies.
Kitchen timer example.
Design methodologies
Every company has its own design
methodology.
Methodology depends on:
size of chip;
design time constraints;
cost/performance;
available tools.
Generic design flow
architectural
simulation
floorplan
register-transfer
design
logic
design
circuit
design
layout
functional/
performance
verification
testability
detailed
specs
tapeout
Specification and planning
Driven by contradictory impulses:
customer-centric concerns about cost,
performance, etc.;
forecasts of feasibility of cost and
performance.
Features, performance, power, etc.
may be negotiated at early stages;
negotiation at later stages creates
problems.
Estimation and planning
Estimation techniques vary with
module:
memories may be generated once size is
known;
data paths may be estimated from
previous design;
controllers are hard to estimate without
details.
Estimates must include speed, area,
power.
Floorplanning and budgeting
The purpose of early floorplanning is
to establish budgets for each major
component: area, delay, power, etc.
The project leader must ensure that
budgets are met at all times. If it
becomes clear that meeting a budget
for a component is impossible, the
floorplan must be redone ASAP.
Logic design
For controllers, good state
assignment is usually requires CAD
tools.
Logic synthesis is an option:
very good for non-critical logic;
can work well for speed-critical logic.
Logic synthesis system may be
sensitive to changes in the input
specification.
Circuit/layout design
Tasks:
size transistors;
draw layout.
Alternative design styles:
full custom logic (very tedious);
standard cell.
Full custom most likely for datapaths,
least likely for random logic off critical
path.
Design validation
Must verify:
layout (design rule check = DRC);
circuit performance;
clock distribution;
functionality;
power consumption / power bussing.
Testing
Automatic test pattern generation =
ATPG.
Must verify that circuit can be tested,
generate a compact set of
manufacturing test vectors.
Test vectors often comprised of
vectors taken from simulation +
ATPG-generated vectors.
Tapeout
Tapeout: generating final files for
masks. Shipped to mask-making
house.
Pre-tapeout verification is importance
since it will take months to get results
from fab.
Tapeout party follows. Size of party
depends on importance of chip design
project.
Kitchen timer chip
Simple example which illustrates
overall design process.
Kitchen timer keeps two independent
timers:
set minutes, seconds.
go, clear;
Not performance-sensitive; is power-
sensitive.
Kitchen timer system
timer
chip
timer 1 timer 2 go
minutes seconds clear
seconds
Timer chip architecture sketch
buttons
enable
segments
buzzer
controller
timer 1 timer 1
buzz
display
Functional simulator
Given in Appendix C.
Operates in event-driven style:
seconds clock;
button depressions.
Provides basic functional verification,
allows exercising major architectural
components.
Major design decisions
Use binary-coded decimal (BCD) to
represent times:
allows direct display of timer register
values;
requires a few more registers than binary,
but BCD/7-segment decoder is much
smaller than binary/7-segment decoder.
Use scanned displaysend only one
digit at a time to display to reduce
wiring between components.
Kitchen timer component
hierarchy
timer chip
controller buzz timers display
timer 1 timer 2
Component inventory
Timers: Holds time in register; can
increment, decrement, clear.
Inputs: incr_seconds[2], incr_minutes[2],
seconds, go[2], digit_select[2], timer.
Outputs: done, digit[4].
Display: Cycles through displayed
digits.
Inputs: digit[4].
Outputs: digit_select[2], enable[4],
segments[7].
Component inventory (contd)
Buzz: Enables buzz signal until stop.
Inputs: done, stop. Outputs: buzz.
Controller: Generates all required
control signals.
Inputs: timer_1, timer_2, minutes_in,
seconds_in, clear_in, go_in.
Outputs: timer_select, incr_minutes, go,
clear, output_select.
Component size estimates
One timer: 14 latches and about 30
gates.
Timers: 28 latches and 70 gates.
Display: 4 latches and about 15
gates.
Buzz: 2 latches and 2 gates.
Controller: 8 latches and 20 gates.
Kitchen timer initial floorplan
timers
display
controller
buzz
4
4
4
1
4
7
1
Topics
CAD systems.
Simulation.
Placement and routing.
Layout analysis.
CAD systems
Tools arent very useful if they dont
talk to each other.
Design interchange languages:
VHDL (TM), Verilog (TM) (function and
structure);
EDIF (netlists);
GDS, CIF (masks).
CAD tool interactions
database
tool 1 tool 2
tool 3 tool 4
database (hub-and-spoke) translator
tool 1 tool 2
tool 3 tool 4
xlate a
xlate c
xlate b
xlate e
xlate d
Back annotation
Often want to iteratively improve
design.
Back annotation updates a more-
abstract design with information from
later design stages.
Example: annotate logic schematic with
extracted parasitic Rs and Cs.
Back annotation requires tools to
know more about each other.
Event-driven simulation is designed
for digital circuit characteristics:
small number of signal values;
relatively sparse activity over time.
Event-driven simulators try to update
only those signals which change in
order to reduce CPU time
requirements.
Event-driven simulator
structure
An event is a change in a signal
value.
A timewheel is a queue of events.
Simulator traces structure of circuit to
determine causality of eventsevent
at input of one gate may cause new
event at gates output.
example
A
B
C
D
logic network behavior
example, contd
Events at primary inputs:
A changes at t=1;
B changes at t=2.
Immediate causality:
C changes at t=3 when both inputs to
NOR are 0.
Event propagation:
D changes at t=4.
Delay models
Unit-delay simulators assume that
each component has a one-unit delay.
Model function but not performance.
Variable-delay simulators allow each
component to have its own delay.
Accuracy of performance estimates from
variable-delay simulators depends on
how well circuits can be extracted to
digital model.
Switch simulation
Special type of event-driven
simulation optimized for MOS
transistors.
Treats transistor as switch. Takes
capacitance into account to model
charge sharing, etc.
Can also be enhanced to model
transistor as resistive switch.
Switch simulation example
Switch simulation example,
contd
Node g may be connected to either
power supply, but signals on that
node are terminated by gate of
transistor.
To solve for values of a and b nodes,
must first solve for value of g node.
If g=1, then a=b.
If g=0, other parts of circuit determine a
and b independently.
Switch simulation and charge
sharing
Closed transistor connects source and
drain nodes. Want to determine
voltages of source/drain nodes taking
into account capacitance.
Capacitance determines node size.
Use size of connected nodes to
determine new value of nodes.
Result may be X (unknown).
Layout synthesis
Two critical phases of layout design:
placement of components on the chip;
routing of wires between components.
Placement and routing interact, but
separating layout design into phases
helps us understand the problem and
find good solutions.
Placement metrics
Quality metrics for layout:
area;
delay.
Area and delay deterined in part by
wiring.
How do we judge a placement
without wiring? Estimate wire length
without actually performing routing.
Wire length as a quality metric
bad placement good placement
Wire length measures
Estimate wire length by distance
between components.
Possible distance measures:
Euclidean distance (sqrt(x
2
+ y
2
));
Manhattan distance (x + y).
Multi-point nets must be broken up
into trees for good estimates.
Placement techniques
Can construct an initial solution,
improve an existing solution.
Pairwise interchange is a simple
improvement metric:
Interchange a pair, keep the swap if it
helps wire length.
Heuristic determines which two
components to swap.
Placement by partitioning
Works well for components of fairly
uniform size.
Partition netlist to minimize total wire
length using min-cut criterion.
Partitioning may be interpreted as 1-
D or 2-D layout.
Min-cut bisecting partitioning
partition 1 partition 2
A
B
C
D
3 nets
1 net
Min-cut bisecting partitioning,
contd
Swapping A and B:
B drags 1 net;
A drags 3 nets;
total cut increase: 4 nets.
Conclusion: probably not a good
swap, but must be compared with
other pairs.
Kernighan-Lin algorithm
Compute min cut criterion:
count total net cut change.
Algorithm exchanges sets of nodes to
perform hill-climbingfinding
improvements where no single swap
will improve the cut.
Recursively subdivide to determine
placement detail.
Simulated annealing
Powerful but CPU-intensive
optimization technique.
Analogy to annealing of metals:
temperature determines probability of a
component jumping position;
probabilistically accept moves.
start at high temperature, cool to lower
temperature to try to reach good
placement.
Routing
Major phases in routing:
global routing assigns nets to routing
areas;
detailed routing designs the routing
areas.
Net ordering is a major problem.
Order in whch nets are routed
determines quality fo result. Net
ordering is a heuristic.
Maze routing
Will find shortest path for a single
wire, if such a path exists.
Two phases:
Label nodes with distance, radiating from
source.
Use distances to trace from sink to
source, choosing a path that always
decreases distance to source.
Maze routing example
Detailed routing
Dogleg router breaks net into multiple
segments as needed.
Try to minimize number of dogleg
segments per net to minimize
congestion for future nets.
One good heuristicuse left-edge
criterion on each dogleg segment to
fill up the channel.
Rivest-Fiduccia channel router
Routes from left to right. Assigns all nets
that cross the current column to tracks.
Heuristics:
Make connections to pins.
Add jogs to put multi-track net into one
track.
Add jogs to reduce distance in multi-
track nets.
Add jogs to move net toward next pin.
Add tracks when necessary.
YACR2
Tries to minimize number of vias as
well as number of tracks.
Temporarily satisfies vertical
constraints by adding blank space
between pins.
Eliminates blank space ater by adding
jobs.
May route in both directions on same
layer.
Layout analysis
Test design rules using Boolean
combinations of masks, grow/shrink.
M1
M2
M1 and M2
not (M1 or M2)
M1
M2
Scan line algorithm
Mark each edge of polygon with
direction.
Sweep scan line across layout.
At each point on scan line, count
number of left-hand and right-hand
edges to determine what rectangle
that point is in.
Scan line algorithm example
M1
M2
sweep
a
b

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