Interrupts

Introduction to Interrupt processing

• This technique will cover
– Interrupt structures of Intel family of
microprocessors
– Operation of software interrupt instructions
INT, INTO,INT3 and BOUND
– IF Flag bit and its impact on interrupt structure
– Trap interrupt flag and operation of trap
generated tracing
– Interrupt service procedure
– Intel 8259A programmable interrupt controller
 Purpose of interrupts
• Useful when interfacing I/O devices that
provide / require data at relatively LOW
data transfer rates
• The slow speed devices takes
considerable CPU time and processor
bandwidth if polling technique is used
• Alternatively this technique gets the
attention of processor, when ever it needs
attention for an I/O transaction
•Interrupt processing is an alternative to polling. 
 Operation of interrupts in Intel
family of microprocessors
• Two hardware pins that request interrupts
– INTR
– NMI
• One hardware pin that acknowledges the interrupt
– /INTA
• In addition to these pins it has software interrupts
internally generated to oversee and control the CPU
processes
– INT, INTO, INT3 and BOUND
• Two flag bits IF (interrupt Flag ) and TF ( Trap Flag )
• And special return instruction IRET or IRETD
(80386/486/ Pentium/ Pentium 4)
Interrupt vectors and Vector tables
• These locations are reserved locations
which directs the course of the programs
• First 1024 bytes of memory at addresses
000000H – 0003FFH
• Organized as 4 byte interrupt vectors of
256 vectors
• An interrupt vector contains the address of
( segment and offset ) of the interrupt
service procedure
 Details of interrupt vectors
• First five Interrupt vectors are identical to all Intel
microprocessors for upward and downward
compatibility
• First 32 vectors are reserved for Intel processors
interrupt processing
• The remaining 224 vectors are left for user
applications interface
• Vectors are 4 bytes long and first two bytes
contains offset address and last two bytes
contains segment address
Interrupt Vector Table
 Details of Interrupt vectors
• Type 0
– Divide Error ; when results of division
overflows or attempt to divide by 0
• Type 1
– Single step or trap; If TF is set, it occurs after
execution of each instruction
• Type 2
– Non maskable hardware interrupt; Logic 1 at
NMI pin
Details of Interrupt vectors (Contd )
• Type 3
– One Byte interrupt; As a result of executing INT3
instruction this vector points out to ISP- used for
break point in the debugging the program
• Type 4
– Overflow; A special vector used with INTO instruction;
interrupts the program of OF is set
• Type 5
– Bound instruction trigger this vector if it is beyond
bound limit
Details of Interrupt vectors (Contd )
• Type 6
– Invalid opcode ; occurs when undefined opcode is
encountered
• Type 7
– Coprocessor not available; occurs when a
coprocessor is not found in system and tries to
execute ESC and WAIT instructions
• Type 8
– Double Fault; Activated when two separate interrupts
occur during same instruction; A resolution vector
Details of Interrupt vectors (Contd )
• Type 9
– Co processor segment over run; occurs when
ESC ins of Coprocessor memory operand
exceeds offset address of FFFFH
• Type 10
– Invalid task state segment
• Type 11
– Segment not present; occurs when P bit (P=0)
in the descriptor
Details of Interrupt vectors (Contd )
• Type 12
– Stack segment overrun
• Type 13
– General protection ; occurs for most
protection violations in 80286 – Pentium 4
mode system
• Type 14
– Page fault in 80386 , 486 and Pentium4
micros
Details of Interrupt vectors (Contd )
• Type 15
– unassigned
• Type 16
– Coprocessor error
• Type 17
– Alignment check ; indicates that for word and
double word data are addressed at odd
memory locations- 80486 and Pentium-
Pentium 4
Details of Interrupt vectors (Contd )
• Type 18
– Machine Check; activates a system memory
management mode interrupt in Pentium –
Pentium 4 microprocessors
 Interrupt Instructions
• BOUND rrr, DATA
– Compares Register with two words of memory data and If <rrr>< data and
Data1;raise type5. If <rrr> > data 2 and data 3 ; raise type 5
• INTO
– Checks the overflow Flag ( OF) ; If 1 , it calls ISP whose address is stored in type
4 location
• INT n
– Calls the ISP pointed by Vector n
• (e.g) INT 80 H or INT 128 calls ISP at locations 000200H- 000203H
• To get the start location of vector address multiply the number by 4 and get the vector
address
• IRET
– Retrieves the return address flags from the stack
– Removes 6 bytes from stack ; 2 for the IP, two for the CS, and 2 for the flags
• IRETD
– For 386 – Pentium4 for EFLAG ( 32 bits ) and 23 bits EIP in the protected mode
 Operation of Real mode Interrupt
If One or more interrupt condition is present
1. Contents of Flag registers pushed onto stack
2. Both IF and TF flags are cleared. This disables the INTR pin and
Trap or single step
3. The contents of Code Segment Reg (CS) > stack
4. The contents of Instruction Pointer (IP) > stack
5. The interrupt vector contents are fetched and placed into both IP
and CS so that next instruction executes at ISP addressed by
the vector
6. The IRET instruction enables the further interrupts and restore
CS , IP and Flags
7. Normal interrupts return to IP+1 for execution ; In some cases
like type 0,5,6,7,8,10,11,12,13 points to same offending
instruction to retry and increment should be in ISP
 Operations of protected mode
interrupt
• Interrupts have the same assignments as in real
mode, but vector table uses
– 256 Interrupt Descriptor Tables (IDT) in the same
order
– Each descriptor is 8 byte in length
– Can be located any memory location in the system
pointed by IDT address Register
– Each entry in the IDT contains the address of ISP in
the form of the segment Register, 32 bit offset
address
– It also contains P bit and DPL bits ( 2 bits ) for priority
of the interrupt
 The protected mode Interrupt
descriptor table
Real mode interrupt vectors can be converted into protected mode interrupts

- By copying the ISP addresses of Int vector and convert them to 32 bit addresses
- And storing it in IDT

The only difference is the Microprocessor accesses the IDT instead of vector table

7 Offset ( A31- A16) 6

5 P DP L 01110 00H 4

3 Segment selector 2

1 Offset ( A15- A0) 0

 Interrupt Flag bits
• Interrupt Flag (IF) and Trap Flag (TF) are cleared after the flag reg
are stacked during the interrupt

O D I T S Z

15 10 9 8 7 6 5 0

• If IF bit is set, unmask interrupt pin

• IF TF bit is set, Trap interrupt occurs after each instruction
• The interrupt flag are set and cleared by STI and CLI instruction,
• No instruction for Trap Flag, but can be modified in IDT on the stack
and Pop it back
 Hardware interrupts
• Two Hardware interrupt inputs NMI and INTR
• NMI >>>>type 2 interrupt occurs and is internally
decoded;
– edge triggered (0 to 1 transition
– And remain in logic 1 till it is recognised
– NMI pin must be at logic 0 for at least two clocks
• INTR >>>> to be externally decoded and to
select a vector ranging between 20H to FFH
• /INTA signal for acknowledging Interrupt and
also used for loading the vector address to the
processor
 Hardware interrupts - INTR and
/INTA
• Level sensitive

INTR

/INTA

/LOCK

/INTA

D7- D0 Ignored Vector number

 Hardware interrupts - INTR and
/INTA
• Simple and least expensive
– Pull up data bus to high and NC to /INTA
• For flexible vector addresses use Tri-state
bus buffer and thumbwheel switches to
ground the pull up resistors
– /INTA for enabling the LOW Data bus
 Hardware Interrupts
Simplest method of generating an
interrupt vector:
Tri-state Buffer for Generating
the Interrupt Vector
 8255 interface with Keyboard
interrupt
• Interrupt scheme and structure
• Interrupt programming
• A student can volunteer for a short
seminar 10 minutes on this topic
An Example 82C55 Interrupt
Configuration
 Expanding the interrupt structure
• Gated interrupt, and expand the interrupts by buffering
the interrupt sources
– Unique interrupt vectors for all combinations
– Interrupt priority to be resolved by specified vector addresses for
interrupts
– All 128 vectors locations are used for combinations , so not cost
effective
– Simple expansion for dedicated applications
• Daisy chained
– Only one interrupt vector , but task of determining the priority lies
with ISP and so longer ISP execution time.
– Longer time to respond for interrupts, but highly flexible.
 Handling more than 1 IRQ

•If any of IRQx goes low, the NAND goes low requesting an interrupt. 
 
•Note that if more than one IRQ goes low, a unique interrupt vector is generated and an 
interrupt priority needs to be defined. 
•The Interrupt Vector table must be expanded to accommodate this
Daisy-Chained Mechanism for
Multiple IRQs
 Expanding interrupts with 8259A
Programmable Interrupt controller
• General descriptions of 8259A ( PIC )
– Programmable interrupt vectors
– In-service registers
– Priority resolver logic
– Directly interfaceable with /CS, /IOWR and /IORD
– A0 address line selects different command words
within 8259A
– CAS2 – CAS 0 lines for cascading multiple 8259A as
master – slave
– SP/~EN for DB buffer enable for large systems in
buffered mode and Master / slave in typical systems
 8259A Programmable Interrupt
Controller
•The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. 
 
•It can be expanded to 64 interrupt requests by using one master 8259A and 8 slave units. 
 8259A Programmable Interrupt
Controller
• The meaning of the other connections:
• WR
– Connects to a write strobe signal (one of 8 for the Pentium).
• RD
– Connects to the IORC signal.
• INT
– Connects to the INTR pin on the microprocessor.
• INTA
– Connects to the INTA pin on the microprocessor.
• A0
– Selects different command words in the 8259A.
• CS
– Chip select - enables the 8259A for programming and control.
• SP/EN
– Slave Program (1 for master, 0 for slave)/Enable Buffer (controls the data bus trancievers
when in buffered mode).
• CAS2-CAS0
– Used as outputs from the master to the slaves in cascaded system
8259A Programmable Interrupt
Controller
•A single 8259A connected in the 8086. 
8259A Programmable Interrupt
Controller cascaded( buffered )
 Programming the 8259A
•Programmed by Initialization (ICWs) and Operation (OCWs) Command Words. 
 
•There are 4 ICWs. 
•At power­up, ICW1, ICW2 and ICW4 must be sent. 
•If ICW1 indicates cascade mode, then ICW3 must also be sent. 
  Call address interval
e.ICW1: 1 = interval of 4; 0 For 8

•LTIM indicates if IRQ lines are positive edge­triggered or level­triggered
 Programming the 8259A

•ICW2:

•These bits determine the vector numbers used with the IRQ inputs. 
•For example, if programmed to generate vectors 08H­0FH, 08H is placed into 
these bit positions. 
•ICW3:
 Programming the 8259A

•ICW4:

•Fully nested mode allows the highest­priority interrupt request from a slave to be 
recognized by the master while it is processing another interrupt from a slave. 
 
•AEOI, if 1, indicates that an interrupt automatically resets the interrupt request 
bit, otherwise OCW2 is consulted for EOI processing. 
 Programming the 8259A
•The Operation Command Words (OCWs) are used to direct the operation of the 8259A. 
b.OCW1:

•OCW1 is used to read or set the interrupt mask register. 
•If a bit is set, it will turn off (mask) the corresponding interrupt input. 
•OCW2:

•Only programmed when the AEOI mode in ICW4 is 0. 
•Allows you to control priorities after each interrupt is processed. 
 Programming the 8259A
•OCW2:

•Non­specific EOI: Here, the ISR sets this bit to indicate EOI. The 8259A 
automatically determines which interrupt was active and re­enables it and lower 
priority interrupts. 
•Specific EOI: ISR resets a specific interrupt request given by L2­L0. 
•Rotate commands cause priority to be rotated w.r.t. the current one being 
processed. 
•Set priority: allows the setting of the lowest priority interrupt (L2­L0). 
 Programming the 8259A

•OCW3:

•If polling is set, the next read operation will read the poll word. 
•If the leftmost bit is set in the poll word, the rightmost 3 bits indicate the 
active interrupt request with highest priority. 
•Allows ISR to service highest priority interrupt. 
 
•There are three status registers, Interrupt Request Register (IRR), In­Service 
Register (ISR) and Interrupt Mask Register (IMR). 
e.IRR: Indicates which interrupt request lines are active.
f.ISR: Level of the interrupt being serviced.
g.IMR: A mask that indicates which interrupts are on/off.
 Programming the 8259A
•ISR update procedure with rotating priority configured.