8evlew ueslgn AbsLracLlon Levels

SYSTEM
GATE
CIRCUIT
V
out
V
in
CIRCUIT
V
out
V
in
MODULE
+
DEVICE
n+
S D
n+
G
8evlew 1he MCS 1ranslsLor
Gate oxide
n+
Source Drain
p substrate
Bulk (Body)
p+ stopper
Field-Oxide
(SiO
2
) n+
Polysilicon
Gate
L
W
MCS lnverLer
A llrsL Look
V
DD
V
out
C
L
V
in
MCS lnverLer
SLeady SLaLe 8esponse
V
DD
R
n
V
out
= 0
V
in
= V
DD
V
DD
R
p
V
out
= 1
V
in
= 0
V
OL
= 0
V
OH
= V
DD
V
M
= f(R
n
, R
p
)
MCS roperLles
W lull rallLorall swlng hlgh nolse marglns
Loglc levels noL dependenL upon Lhe relaLlve devlce slzes
LranslsLors can be mlnlmum slze raLloless
W Always a paLh Lo v
dd
or Cnu ln sLeady sLaLe low
ouLpuL lmpedance (ouLpuL reslsLance ln krange)
large fanouL (albelL wlLh degraded performance)
W Lremely hlgh lnpuL reslsLance (gaLe of MCS
LranslsLor ls near perfecL lnsulaLor) nearly zero
sLeadysLaLe lnpuL currenL
W no dlrecL paLh sLeadysLaLe beLween power and
ground no sLaLlc power dlsslpaLlon
W ropagaLlon delay funcLlon of load capaclLance and
reslsLance of LranslsLors
8evlew ShorL hannel lv loL
(nMCS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
DS
(V)
X 10
-4
V
GS
= 1.0V
V
GS
= 1.5V
V
GS
= 2.0V
V
GS
= 2.5V
NMOS transistor, 0.25um, L
d
= 0.25um, W/L = 1.5, V
DD
= 2.5V, V
T
= 0.4V
8evlew ShorL hannel lv loL
(MCS)
-1
-0.8
-0.6
-0.4
-0.2
0
0 -1 -2
V
DS
(V)
X 10
-4
V
GS
= -1.0V
V
GS
= -1.5V
V
GS
= -2.0V
V
GS
= -2.5V
PMOS transistor, 0.25um, L
d
= 0.25um, W/L = 1.5, V
DD
= 2.5V, V
T
= -0.4V
All polarities of all voltages and currents are reversed
1ransformlng MCS lv Llnes

DSp
= -
DSn
V
GSn
= V
in
; V
GSp
= V
in
- V
DD
V
DSn
= V
out
; V
DSp
= V
out
- V
DD
V
out

Dn
V
GSp
= -2.5
V
GSp
= -1
Mirror around x-axis
V
in
= V
DD
+ V
GSp

Dn
= -
Dp
V
in
= 1.5
V
in
= 0
V
in
= 1.5
V
in
= 0
Horiz. shift over V
DD
V
out
= V
DD
+ V
DSp
Want common coordinate set V
in
, V
out
, and
Dn
MCS lnverLer Load Llnes
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
out
(V)
X 10
-4
V
in
= 1.0V
V
in
= 1.5V
V
in
= 2.0V
V
in
= 2.5V
0.25um, W/L
n
= 1.5, W/L
p
= 4.5, V
DD
= 2.5V, V
Tn
= 0.4V, V
Tp
= -0.4V
V
in
= 0V
V
in
= 0.5V
V
in
= 1.0V
V
in
= 1.5V
V
in
= 0.5V
V
in
= 2.0V
V
in
= 2.5V
V
in
= 2V
V
in
= 1.5V
V
in
= 1V
V
in
= 0.5V
V
in
= 0V
PMOS NMOS
MCS lnverLer v1
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
in
(V)
V
o
u
t
(
V
)
MCS lnverLer v1
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
in
(V)
V
o
u
t
(
V
)
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS sat
PMOS sat
NMOS res
PMOS sat
NMOS res
PMOS off
MCS lnverLer
SwlLch Model of uynamlc 8ehavlor
V
DD
R
n
V
out
C
L
V
in
= V
DD
V
DD
R
p
V
out
C
L
V
in
= 0
MCS lnverLer
SwlLch Model of uynamlc 8ehavlor
V
DD
R
n
V
out
C
L
V
in
= V
DD
V
DD
R
p
V
out
C
L
V
in
= 0
Gate response time is determined by the time to charge C
L
through R
p
(discharge C
L
through R
n
)
8elaLlve 1ranslsLor Slzlng
W When deslgnlng sLaLlc MCS clrculLs
balance Lhe drlvlng sLrengLhs of Lhe
LranslsLors by maklng Lhe MCS secLlon
wlder Lhan Lhe nMCS secLlon Lo
malmlze Lhe nolse marglns and
obLaln symmeLrlcal characLerlsLlcs
SwlLchlng 1hreshold
r=1
Sizing
For symmetrical VTC
r Vm Wp n general
And vice versa
Sizing set to the desired
Vm

NMOS
PMOS
SwlLchlng 1hreshold
W v
M
where v
ln
v
ouL
(boLh MCS and nMCS ln
saLuraLlon slnce v
uS
v
CS
)
v
M
rv
uu
/(1 + r) where r k
p
v
uSA1p
/k
n
v
uSA1n
W SwlLchlng Lhreshold seL by Lhe raLlo r whlch
compares Lhe relaLlve drlvlng sLrengLhs of Lhe
MCS and nMCS LranslsLors
W WanL v
M
v
uu
/2 (Lo have comparable hlgh and
low nolse marglns) so wanL r 1
(W/L)
p
k
n
'v
uSA1n
(v
M
v
1n
v
uSA1n
/2)
(W/L)
n
k
p
'v
uSA1p
(v
uu
v
M
+v
1p
+v
uSA1p
/2)
=
SwlLch 1hreshold ample
W ln our generlc 023 mlcron MCS process uslng Lhe
process parameLers from sllde L0323 a v
uu
23v and a
mlnlmum slze nMCS devlce ((W/L)
n
of 13)
V
T0
(V) (V
0.5
) V
DSAT
(V) k'(A/V
2
) 2(V
-1
)
NMOS 0.43 0.4 0.63 115 x 10
-6
0.06
PMOS -0.4 -0.4 -1 -30 x 10
-6
-0.1
(W/L)
p
(W/L)
n
=
SwlLch 1hreshold ample
W ln our generlc 023 mlcron MCS process uslng Lhe
process parameLers v
uu
23v and a mlnlmum slze
nMCS devlce ((W/L)
n
of 13)
V
T0
(V) (V
0.5
) V
DSAT
(V) k'(A/V
2
) 2(V
-1
)
NMOS 0.43 0.4 0.63 115 x 10
-6
0.06
PMOS -0.4 -0.4 -1 -30 x 10
-6
-0.1
(W/L)
p
115 x 10
-6
0.63 (1.25 0.43 0.63/2)
(W/L)
n
-30 x 10
-6
-1.0 (1.25 0.4 1.0/2)
= x x
= 3.5
(W/L)
p
= 3.5 x 1.5 = 5.25 for a V
M
of 1.25V
SlmulaLed lnverLer v
M
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
0 1 10
(W/L)
p
/(W/L)
n
V
M
is relatively
insensitive to variations in
device ratio
setting the ratio to 3, 2.5
and 2 gives V
M
's of 1.22V,
1.18V, and 1.13V
ncreasing the width of
the PMOS moves V
M
towards V
DD
ncreasing the width of
the NMOS moves V
M
toward GND
.1
Note: x-axis is semilog
~3.4
nolse Margln
approximation
nolse Marglns ueLermlnlng v
lP
and v
lL
0
1
2
3
VIL VIH
V
in
V
OH
= V
DD
V
M
By definition, V
H
and V
L
are
where dV
out
/dV
in
= -1 (= gain)
V
OL
= GND
A piece-wise linear
approximation of VTC
NM
H
= V
DD
- V
H
NM
L
= V
L
- GND
Approximating:
V
H
= V
M
- V
M
/g
V
L
= V
M
+ (V
DD
- V
M
)/g
So high gain in the transition
region is very desirable
Caln
Technology
parameters
Device is functioning in saturation

dn

dp
gain
Caln ueLermlnaLes
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
0 0.5 1 1.5 2
V
in Gain is a strong function of the
slopes of the currents in the
saturation region, for V
in
= V
M
(1+r)
g ----------------------------------
(V
M
-V
Tn
-V
DSATn
/2)(2
n
- 2
p
)
Determined by technology
parameters, especially channel
length modulation (2). Only
designer influence through
supply voltage and V
M
(transistor
sizing).
MCS lnverLer v1 from SlmulaLlon
0.25um, (W/L)
p
/(W/L)
n
= 3.4
(W/L)
n
= 1.5 (min size)
V
DD
= 2.5V
V
M
1.25V, g = -27.5
V
L
= 1.2V, V
H
= 1.3V
NM
L
= NM
H
= 1.2
(actual values are
V
L
= 1.03V, V
H
= 1.45V
NM
L
= 1.03V & NM
H
= 1.05V)
Output resistance
low-output = 2.4k
high-output = 3.3k
lmpacL of rocess varlaLlon on v1
urve
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
in
(V)
V
o
u
t
(
V
)
Nominal
Good PMOS
Bad NMOS
Bad PMOS
Good NMOS
Process variations (mostly) cause a shift in the switching threshold
Behavior remains
unchanged
For good one
Scallng Lhe Supply volLage
Vm
&
Scallng Lhe Supply volLage
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
in
(V)
V
o
u
t
(
V
)
Device threshold voltages are
kept (virtually) constant
0
0.05
0.1
0.15
0.2
0 0.05 0.1 0.15 0.2
V
in
(V)
V
o
u
t
(
V
)
Gain=-1
Device threshold voltages are
kept (virtually) constant
erformance of MCS lnverLer
1he dynamlc 8ehavlor
CL has to be as small as possible for high
performance
Major component of CL
CaLeuraln capaclLance
Assumption: V
in
is driven by an ideal voltage source with zero rise and fall
timesWe will account for capacitances connected to the output node
Assumption: All capacitance are lumped together into a single capacitor C
L
,
located between V
out
and GND.
ulffuslon apaclLance
&nfortunately very non-linear
So we linearize it!
Wlrlng apaclLance
W Depends on the length, width of the
connecting wire,
W And also on the number of fan-out gates and
their distance from the driving gate
W Gaining mportance!
CaLe capaclLance

L
C
L
from High-low and low-high are
approx same
ropagaLlon uelay 1
sL
order Analysls
ntractable, so we
can try switch
model
:
:
:

9
9
9
4:9
0
0
0 '

ropagaLlon uelay 1
sL
order Analysls
To ncrease
performance
ropagaLlon uelay (ueslgn perspecLlve)
W 3-3.5 sizing although ensures symmetrical VTC and similar
t
pHL
and t
pLH
(R
eqn
=R
eqp
) but =/=> tp(min)
W (reason) widening of PMOS although improves t
pLH
but
degrades t
pHL
(larger parasitic capacitance)
W need to optimize
3
5


.
$$&MPTION:
PMOS times larger
than NMOS
C
dp1
=C
dn1
; C
gp2
=C
gn2
; R'
eqp
=R
eqp
/
CpLlmal performance (slzlng)
Slzlng lnverLer for performance
Sizing
Assume symmetrical nverter
Slzlng lnverLer for performance
Slzlng chaln of lnverLers
Both are
proportionaI to
gate sizing
f
1
=f
2
=f
3
....=f
N
f
1
f
2
f
3
....f
N
=f
N
=C
L
/C
g,1
=F
Overall fan-out
Slzlng chaln of lnverLers
for
N
&vice versa

tp can be
optimized

/
/9
5
CpLlmlzlng n
SLaLlc MCS eLenslon Lo sLaLlc MCS lnverLer
omplemenLary MCS
W Transistor can be thought of as a switch, controlled by gate
W PDN NMOS, and P&N PMOS
W Rules: NMOS series=AND, NMOS parallel=OR (PMOS series=NOR, PMOS
parallel=NAND
W De Morgan's theorem is applied (series parallel and vice versa)
WCMOS is naturally inverting NAND, NOR, XNOR are naturally
implemented
P&N PDN
SLaLlc properLles MCS
Stronger V
Tn
Strong pull-up
ropagaLlon uelay
A=B=10
A0, B=1 or
A=1, B0
Worst case
A=B=01
LH
HL
R
N
=R
p
/2 width should be twice
PMOS:
NMOS:
8aLloed Loglc
WReduced number of transistor.
WVOL is not equal to zero
WStatic power dissipation.
ulfferenLlal ascode volLage swlLch Loglc
(uvSL)