DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : K.john Samuel
Designation : HECES
Branch : ECE
Institute : Govt. Polytechnic, Masabtank, Hyd.
Semester : III Semester
Subject : Digital Electronics
Subject Code : EC – 304
Topic : Basics of Digital Electronics
Duration : 50 Mts.
Sub-Topic : TTL NAND GATE
Teaching Aids : PPT Animations
EC304.17 1
Objectives
On completion of this period, you would be able to

• Draw the TTL NAND gate open collector circuit

• Know its operation

• Draw the TTL NAND gate Totem Pole circuit.

• Know its operation

EC304.17 2
 ?

• Name the Universal Gates?

• Why they are so called ?

• What are the semiconductor devices used to construct the

gates.

EC304.17 3
Recap

• Transistor-Transistor logic is a widely used family.

• TTL is fast, in expensive and easy to use.

• Bipolar Transistor Technology is used for MSI & SSI

( medium scale integration and small scale
integration).

• Used to build all kinds of digital circuits and systems.

EC304.17 4
TTL NAND GATE

= AB

EC304.17 5
Working of TTL NAND Gate

• The simplest form of TTL NAND Gate is shown.

• The emitter terminals of transistor Q1 are the input terminals.

• The collector of Q3 is the output terminal.

• If one of the inputs is zero, the corresponding emitter junction

is forward biased.

• Collector junction is also biased, hence transistor Q1 goes

into saturation.
EC304.17 6
Working of TTL NAND Gate (Contd)

• The base of Q2 is at a low voltage.

• Q2 is off, the output ‘Y’ is high.

• If both the inputs are high, both the emitter junctions are
driven to reverse bias.

• Q1 is cut off, and its collector voltage increases.

• This voltage forward biases Q2

EC304.17 7
Working of TTL NAND Gate (Contd)

• Q2 goes into saturation and output ‘Y’ is low.

• Thus if any or all the inputs are at logic ‘0’ the output is
logic ‘1’.

• If all inputs are at logic ‘1’ the output is at logic ‘0’.

• Hence the circuit functions as a NAND Gate, follows truth

table.

EC304.17 8
Open Collector TTL NAND GATE

= AB

EC304.17 9
Working of Open Collector TTL NAND Gate
• The circuit is similar to previous circuit.

• Transistor Q2 is used as an emitter follower.

• The output of Q2 is fed to the input of transistor Q3.

• Collector of Q3 and Q2 are in phase.

• This circuit needs an external resistor between output

and power supply.
EC304.17 10
• The circuit works properly if an external pull-up resistor
is connected as shown

EC304.17 11
• The disadvantage of open-collector gate is their slow
switching speed.

• The pull-up resistance is few kilo ohms.

• Gives a relatively long time constant, when multiplied by

the stray output capacitance.

• Is worst when output goes from low to high.

EC304.17 12
TTL NAND Gate with Totem Pole Output

EC304.17 13
Working of TTL NAND Gate with Totem-pole
output
• In this circuit Q1 and the 4KΩ resistor act like a 2 input
AND gate

• The remaining circuit acts like an inverter.

• Transistors Q3 & Q4 form a totem-pole connection i.e.,

one npn transistor in series with another.

• With a totem-pole output stage either Q3 or Q4 is on.

EC304.17 14
Working of TTL NAND Gate with Totem-pole
output (Contd).

• When Q3 is ‘on’ output is high.

• When Q4 is ‘on’ output is low .

• If A or B is low, the Q1 conducts and base voltage of Q2

is almost zero.
• Q2 cuts off, hence Q4 goes into cut off.

• Q3 base is high, Q3 acts as an emitter follower, the

output Y’ is high

EC304.17 15
Working of TTL NAND Gate with Totem-pole
output (Contd).
• If A and B are high, Q1 does not conduct, Q2 base goes high.
• Q4 goes into saturation hence output is low.

• The drop across Diode D1 keeps the base emitter diode of Q3

reverse biased .
• Hence Q3 is off or else it conducts slightly when output is low.

• Now only Q4 conducts when output is low.

• Totem pole transistors produce a low output impedance.

EC304.17 16
Working of TTL NAND Gate with Totem-pole
output (Contd).

• When Q3 is conducting the output impedance is

approximately 70 Ω.
• When Q4 is saturated the output impedance is only 12 Ω.
• Hence the output impedance of a totem pole circuit is low.
• Any stray output capacitance is rapidly charged or
discharged through the low output inpedance.
• Hence the output can change quickly from one state to the
other.

EC304.17 17
QUIZ

EC304.17 18
1. TTL is a __________ device

• (i) Fast

(ii) Slow

(iii) Very slow

(iv) None of the above

EC304.17 19
1. Disadvantage of TTL NAND Gate with open collectors is ______

• (i) Slow switching speed

(ii) Fast switching speed

(iii) Slow and fast switching speed

(iv) All of the above

EC304.17 20
3. The use of pull-up resistor is

Proper power supply operation.

4. Use of Diode in totem-pole circuit is

One direction passage of current of output stage transistor.

EC304.17 21
Frequently Asked Questions

1. Draw a TTL NAND Gate with Totem-pole output circuit

and explain.

3. Draw a TTL NAND Gate with Open Collector and

explain.

5. Write the advantages and disadvantages of above two

circuits.

EC304.17 22