DEPARTMENT OF TECHNICAL

EDUCATION ANDHRA PRADESH

 Name : D.RAVI KUMAR
 Designation : Lecturer in ECE

 Branch : Electronics & Communication Engg.

 Institute : Andhra polytechnic
 Year/Semester : III Semester
 Subject : Digital Electronics
 Subject code : CM-305
 Topic : Counters & Registers(7/20,8/20,9/20)
 Sub Topic : Details of TTL counters ICs
 Duration : 50min.
 Teaching aids : PPT & ANIMATIONS
CM-305.47 to 49 1
 Objectives
Upon the completion of the this topic the you would be able
to know

3. The about different TTL counters in IC form.

5. About IC 7490.

7. About IC 7492 and

9. About IC 7493.

CM-305.47 to 49 2
 Recap
• What is a counter?
 A sequential circuit that counts the number of input clock
pulses is called a counter.

• What are the basic elements used in counters.

 Flip-flops.

• How many number of flip-flops are required to design a

counter that counts 12 clock pulses?
 Four.

CM-305.47 to 49 3
 Need for ICs
• To design a counter in laboratory we need

3. More number if flip-flops.

5. Which in turn need more logic gates for each flip-flop.

 This increases the size and complexity of the circuit in

the laboratory.

 Hence it is more convenient to use counter ICs than

counters using flip-flops in the laboratories.

CM-305.47 to 49 4
 List of counter ICs
Some important TTL /CMOS counter ICs
are
IC Numbers Logic family Function

7493 TTL Asynchronous 4-bit counter

74HC393 CMOS Asynchronous 4-bit counter

74190,74192 TTL Synchronous 4-bit UP/DOWN decade counter

40192,74C192 CMOS Synchronous 4-bit UP/DOWN decade counter

7490 TTL Asynchronous decade counter

74390 TTL Asynchronous dual decade counter

74HC193 CMOS Presettable sync 4-bit binary UP/DOWN counter

74LS160A TTL Synchronous Decade counter

CM-305.47 to 49 5
 Details of 7490
 It is an asynchronous 4-bit decade counter.

 It consists of 4 master-slave JK flip-flops connected

internally.

 It provides a divided by two section and a Mod-5

section, hence it is called 2×5 decade counter.

 Each section is selected with the help of separate

clock input on HIGH to LOW transition.

CM-305.47 to 49 6
 Details of 7490
 It consists of two asynchronous master reset inputs
MR1 and MR2 which over ride both clocks and resets
all the flip-flops.

 It also consists of two asynchronous master set inputs

MS1 and MS2 which over ride the clocks and MR inputs
and setting the output to 1001 (nine).

CM-305.47 to 49 7
Timing diagram of the Mod-10 counter

CM-305.47 to 49 8
 Design procedure
• The design of Mod-10 ripple counter can be explained
with help of timing diagram.

• From the timing diagram of previous slide it can be seen

that

 Q0 is complemented on the negative edge of every clock

pulse.

• Hence the external clock is connected to clock input of

the first flip-flop and both J & K =1.

CM-305.47 to 49 9
 Design procedure

 Q1 is complemented if Q3 =0 and Q0 goes from1 to 0.

And Q1 is be cleared if Q3 =1 and Q0 goes from 1 to 0.

• Hence Q0 is to be connected as clock input to 2nd flip-

flop, K=1 and J should become 0 when Q3 is 1 i.e. Q3
is to be connected to J of 2nd flip-flop.

 Q2 must be complemented when Q1 goes from 1 to 0.

• Hence Q1 must be connected to clock input of 3rd flip-

flop with J=K=1.
CM-305.47 to 49 10
 Design procedure
 Finally Q3 must be complemented when Q2Q1=11 and Q0
goes from 1 to 0, and must be cleared if either Q2 or Q1=0
and Q0 goes from 1 to 0.

• Hence 4th flip-flop must be clocked with Q0 ,with its K=1 and
J must be connected from the output of the AND gate
whose inputs are Q1 and Q2.

• By following the above four steps we can design the Mod-10

ripple counter without using the asynchronous inputs as
given below.
CM-305.47 to 49 11
Logic diagram of 7490

CM-305.47 to 49 12
Pin configuration of 7490

CM-305.47 to 49 13
 Working of 7490
 It can be used as a divided by two counter, and as
decade counter.

 If CLK1 of frequency F is given to 1st flip-flop, i.e. to the

14th pin of 7490 clock signal of frequency F/2 will be
available at Q0 i.e. at 12th pin.

 If is Q0 is connected to CLK2 i.e. if 12th pin is connected

to 1st pin and the output is taken at pins 11,8,9 and 12 in
a sequence i.e. Q3Q2Q1Q0 , then it works as decade
counter.
CM-305.47 to 49 14
 Details of 7492
 It is an asynchronous Mod-12 counter.

 It contains four master-slave JK flip-flops.

 All the flip-flops are negative edge triggered flip-flops.

 The flip-flops Q1Q2Q3 forms a 3×2 counter in which Q1Q2

forms a Mod-3 counter.

 It has two clocks CLK1 and CLK2.

CM-305.47 to 49 15
 Details of 7492
 If only CLK2 is applied it works as a Mod-6 counter in the
form of 3×2=6.

 If CLK1 is applied to 1st flip-flop and its output is Q0 is

connected to CLK2 it works as a Mod-12 counter in the
form of 2×3×2=12.

 It also provide two gated RESET inputs RD1 and RD2

 When both of these inputs are HIGH the counter is

RESET to 0000 state by CLR signal.

CM-305.47 to 49 16
Truth table of 7492
Count Q3 Q2 Q1 Q0
Initial 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 1 0 0 0
7 1 0 0 1
8 1 0 1 0
9 1 0 1 1
10 1 1 0 0
11 1 1 0 1
12 0 0 0 0
CM-305.47 to 49 17
Timing diagram of 7492

CM-305.47 to 49 18
Logic diagram of 7492

CM-305.47 to 49 19
Pin configuration of 7492

CM-305.47 to 49 20
 Details of 7493
 It is an asynchronous 4-bit binary counter.

 This device actually consists of a single flip-flop and a 3-

bit asynchronous counter.

 Hence it can be used as a divide-by-2 device using only

the single flip-flop or it can be used as a Mod-8 ripple
counter using only the 3-bit counter operation.

 This chip also provides gated reset inputs R01 and R02.

 When both of these inputs are HIGH the counter resets

to 0000 state by CLR

CM-305.47 to 49 21
Logic diagram of 7493

CM-305.47 to 49 22
Pin configuration of 7493

CM-305.47 to 49 23
 Summary
• In this topic we have drawn the logic diagram of 7490 in
the form of 2×5=Mod-10 counter and understand its pin
configuration.

• We have drawn the logic diagram of 7492 in the form of

2×3×2=Mod-12 counter and understand its pin
configuration.

• And we have drawn the logic diagram of 7493 and

understand its pin configuration.

CM-305.47 to 49 24
 Review questions

1. Draw the internal logic diagram of 7490 and give its

details with pin diagram.

3. Draw the internal logic diagram of 7492 and give its

details with pin diagram.

5. Draw the internal logic diagram of 7493 and give its

details with pin diagram.

CM-305.47 to 49 25